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tcg/tci: Fix big-endian return register ordering

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We expect the backend to require register pairs in
host-endian ordering, thus for big-endian the first
register of a pair contains the high part.
We were forcing R0 to contain the low part for calls.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-21 10:34:21 +10:00
parent c4f4a00ac7
commit 896c76e6ba
1 changed files with 11 additions and 10 deletions
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21
tcg/tci.c
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@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
ffi_call(pptr[1], pptr[0], stack, call_slots); ffi_call(pptr[1], pptr[0], stack, call_slots);
} }
/* Any result winds up "left-aligned" in the stack[0] slot. */
switch (len) { switch (len) {
case 0: /* void */ case 0: /* void */
break; break;
case 1: /* uint32_t */ case 1: /* uint32_t */
/* /*
* The result winds up "left-aligned" in the stack[0] slot.
* Note that libffi has an odd special case in that it will * Note that libffi has an odd special case in that it will
* always widen an integral result to ffi_arg. * always widen an integral result to ffi_arg.
*/ */
if (sizeof(ffi_arg) == 4) { if (sizeof(ffi_arg) == 8) {
regs[TCG_REG_R0] = *(uint32_t *)stack; regs[TCG_REG_R0] = (uint32_t)stack[0];
break;
}
/* fall through */
case 2: /* uint64_t */
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]);
} else { } else {
regs[TCG_REG_R0] = stack[0]; regs[TCG_REG_R0] = *(uint32_t *)stack;
} }
break; break;
case 2: /* uint64_t */
/*
* For TCG_TARGET_REG_BITS == 32, the register pair
* must stay in host memory order.
*/
memcpy(&regs[TCG_REG_R0], stack, 8);
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }