target/arm: Extract HA and HD in aa64_va_parameters
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20221024051851.3074715-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -10470,7 +10470,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMMMUIdx mmu_idx, bool data)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx);
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bool epd, hpd, tsz_oob, ds;
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bool epd, hpd, tsz_oob, ds, ha, hd;
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int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
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ARMGranuleSize gran;
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ARMCPU *cpu = env_archcpu(env);
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@ -10489,6 +10489,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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epd = false;
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sh = extract32(tcr, 12, 2);
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ps = extract32(tcr, 16, 3);
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ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu);
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hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu);
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ds = extract64(tcr, 32, 1);
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} else {
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bool e0pd;
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@ -10514,6 +10516,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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e0pd = extract64(tcr, 56, 1);
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}
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ps = extract64(tcr, 32, 3);
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ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu);
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hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu);
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ds = extract64(tcr, 59, 1);
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if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) &&
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@ -10586,6 +10590,8 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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.hpd = hpd,
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.tsz_oob = tsz_oob,
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.ds = ds,
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.ha = ha,
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.hd = ha && hd,
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.gran = gran,
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};
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}
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@ -1065,6 +1065,8 @@ typedef struct ARMVAParameters {
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bool hpd : 1;
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bool tsz_oob : 1; /* tsz has been clamped to legal range */
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bool ds : 1;
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bool ha : 1;
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bool hd : 1;
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ARMGranuleSize gran : 2;
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} ARMVAParameters;
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