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hw/arm/mps2: New board model mps2-an386

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Implement a model of the MPS2 with the AN386 firmware. This is
essentially identical to the AN385 firmware, but it has a
Cortex-M4 rather than a Cortex-M3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-09-03 21:20:46 +01:00
parent e9b2bfaa64
commit 897d27260a
2 changed files with 34 additions and 8 deletions
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8
docs/system/arm/mps2.rst
View File

@ -1,5 +1,5 @@
Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
================================================================================
Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
================================================================================================
These board models all use Arm M-profile CPUs.
@ -12,6 +12,8 @@ QEMU models the following FPGA images:
``mps2-an385``
Cortex-M3 as documented in ARM Application Note AN385
``mps2-an386``
Cortex-M4 as documented in ARM Application Note AN386
``mps2-an511``
Cortex-M3 'DesignStart' as documented in AN511
``mps2-an505``
@ -21,7 +23,7 @@ QEMU models the following FPGA images:
Differences between QEMU and real hardware:
- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
if zbt_boot_ctrl is always zero)
- QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest

34
hw/arm/mps2.c
View File

@ -15,6 +15,7 @@
* as seen by the guest depend significantly on the FPGA image.
* We model the following FPGA images:
* "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
* "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
* "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
*
* Links to the TRM for the board itself and to the various Application
@ -48,6 +49,7 @@
typedef enum MPS2FPGAType {
FPGA_AN385,
FPGA_AN386,
FPGA_AN511,
} MPS2FPGAType;
@ -82,6 +84,7 @@ typedef struct MPS2MachineState MPS2MachineState;
#define TYPE_MPS2_MACHINE "mps2"
#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
#define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@ -139,9 +142,9 @@ static void mps2_common_init(MachineState *machine)
* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
* call the 16MB our "system memory", as it's the largest lump.
*
* Common to both boards:
* 0x21000000..0x21ffffff : PSRAM (16MB)
* AN385 only:
* AN385/AN386/AN511:
* 0x21000000 .. 0x21ffffff : PSRAM (16MB)
* AN385/AN386 only:
* 0x00000000 .. 0x003fffff : ZBT SSRAM1
* 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
* 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
@ -156,7 +159,7 @@ static void mps2_common_init(MachineState *machine)
* 0x20000000 .. 0x2001ffff : SRAM
* 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
*
* The AN385 has a feature where the lowest 16K can be mapped
* The AN385/AN386 has a feature where the lowest 16K can be mapped
* either to the bottom of the ZBT SSRAM1 or to the block RAM.
* This is of no use for QEMU so we don't implement it (as if
* zbt_boot_ctrl is always zero).
@ -165,6 +168,7 @@ static void mps2_common_init(MachineState *machine)
switch (mmc->fpga_type) {
case FPGA_AN385:
case FPGA_AN386:
make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
@ -192,6 +196,7 @@ static void mps2_common_init(MachineState *machine)
armv7m = DEVICE(&mms->armv7m);
switch (mmc->fpga_type) {
case FPGA_AN385:
case FPGA_AN386:
qdev_prop_set_uint32(armv7m, "num-irq", 32);
break;
case FPGA_AN511:
@ -228,6 +233,7 @@ static void mps2_common_init(MachineState *machine)
switch (mmc->fpga_type) {
case FPGA_AN385:
case FPGA_AN386:
{
/* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
* Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@ -379,7 +385,7 @@ static void mps2_common_init(MachineState *machine)
*/
lan9118_init(&nd_table[0], 0x40200000,
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN385 ? 13 : 47));
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
@ -408,6 +414,17 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
mmc->scc_id = 0x41043850;
}
static void mps2_an386_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
mmc->fpga_type = FPGA_AN386;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
mmc->scc_id = 0x41043860;
}
static void mps2_an511_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@ -434,6 +451,12 @@ static const TypeInfo mps2_an385_info = {
.class_init = mps2_an385_class_init,
};
static const TypeInfo mps2_an386_info = {
.name = TYPE_MPS2_AN386_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an386_class_init,
};
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
@ -444,6 +467,7 @@ static void mps2_machine_init(void)
{
type_register_static(&mps2_info);
type_register_static(&mps2_an385_info);
type_register_static(&mps2_an386_info);
type_register_static(&mps2_an511_info);
}