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Fix target/hppa #635 

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Merge tag 'pull-pa-20211223' of https://gitlab.com/rth7680/qemu into staging

Fix target/hppa #635

# gpg: Signature made Thu 23 Dec 2021 05:47:41 PM PST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-pa-20211223' of https://gitlab.com/rth7680/qemu:
  target/hppa: Fix deposit assert from trans_shrpw_imm

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-12-23 17:53:36 -08:00
parent f18155a207 05bfd4db08
commit 89f3bfa326
1 changed files with 12 additions and 7 deletions
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19
target/hppa/translate.c
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@ -140,6 +140,7 @@
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_gen_extract2_reg tcg_gen_extract2_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
@ -234,6 +235,7 @@
#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_gen_extract2_reg tcg_gen_extract2_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
@ -3204,19 +3206,22 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
if (a->r1 == a->r2) {
if (a->r1 == 0) {
tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
} else if (TARGET_REGISTER_BITS == 32) {
tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
} else if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(t32, t2);
tcg_gen_rotri_i32(t32, t32, sa);
tcg_gen_extu_i32_reg(dest, t32);
tcg_temp_free_i32(t32);
} else if (a->r1 == 0) {
tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
} else {
TCGv_reg t0 = tcg_temp_new();
tcg_gen_extract_reg(t0, t2, sa, 32 - sa);
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
tcg_temp_free(t0);
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
tcg_gen_shri_i64(t64, t64, sa);
tcg_gen_trunc_i64_reg(dest, t64);
tcg_temp_free_i64(t64);
}
save_gpr(ctx, a->t, dest);