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Fix Sparc shift ops (Aurelien Jarno) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2569 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-04-01 15:38:17 +00:00
parent d4218d996d
commit 8a08f9a809
2 changed files with 17 additions and 9 deletions
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19
target-sparc/op.c
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@ -965,38 +965,43 @@ void OPPROTO op_logic_T0_cc(void)
void OPPROTO op_sll(void)
{
T0 <<= T1;
T0 <<= (T1 & 0x1f);
}
#ifdef TARGET_SPARC64
void OPPROTO op_sllx(void)
{
T0 <<= (T1 & 0x3f);
}
void OPPROTO op_srl(void)
{
T0 = (T0 & 0xffffffff) >> T1;
T0 = (T0 & 0xffffffff) >> (T1 & 0x1f);
}
void OPPROTO op_srlx(void)
{
T0 >>= T1;
T0 >>= (T1 & 0x3f);
}
void OPPROTO op_sra(void)
{
T0 = ((int32_t) (T0 & 0xffffffff)) >> T1;
T0 = ((int32_t) (T0 & 0xffffffff)) >> (T1 & 0x1f);
}
void OPPROTO op_srax(void)
{
T0 = ((int64_t) T0) >> T1;
T0 = ((int64_t) T0) >> (T1 & 0x3f);
}
#else
void OPPROTO op_srl(void)
{
T0 >>= T1;
T0 >>= (T1 & 0x1f);
}
void OPPROTO op_sra(void)
{
T0 = ((int32_t) T0) >> T1;
T0 = ((int32_t) T0) >> (T1 & 0x1f);
}
#endif

7
target-sparc/translate.c
View File

@ -1703,7 +1703,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
#endif
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
} else if (xop == 0x25) { /* sll, V9 sllx */
rs1 = GET_FIELD(insn, 13, 17);
gen_movl_reg_T0(rs1);
if (IS_IMM) { /* immediate */
@ -1713,7 +1713,10 @@ static void disas_sparc_insn(DisasContext * dc)
rs2 = GET_FIELD(insn, 27, 31);
gen_movl_reg_T1(rs2);
}
gen_op_sll();
if (insn & (1 << 12))
gen_op_sllx();
else
gen_op_sll();
gen_movl_T0_reg(rd);
} else if (xop == 0x26) { /* srl, V9 srlx */
rs1 = GET_FIELD(insn, 13, 17);