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target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters

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Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
sub-struct. We're going to want id_pfr1 for an isar_features
check, and moving both at the same time avoids an odd
inconsistency.

Changes other than the ones to cpu.h and kvm64.c made
automatically with:
  perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-09-10 18:38:52 +01:00
parent 0ae0326b98
commit 8a130a7be6
7 changed files with 44 additions and 40 deletions
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4
hw/intc/armv7m_nvic.c
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@ -1238,9 +1238,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
"Aux Fault status registers unimplemented\n"); "Aux Fault status registers unimplemented\n");
return 0; return 0;
case 0xd40: /* PFR0. */ case 0xd40: /* PFR0. */
return cpu->id_pfr0; return cpu->isar.id_pfr0;
case 0xd44: /* PFR1. */ case 0xd44: /* PFR1. */
return cpu->id_pfr1; return cpu->isar.id_pfr1;
case 0xd48: /* DFR0. */ case 0xd48: /* DFR0. */
return cpu->isar.id_dfr0; return cpu->isar.id_dfr0;
case 0xd4c: /* AFR0. */ case 0xd4c: /* AFR0. */

20
target/arm/cpu.c
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@ -1659,7 +1659,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
/* Disable the security extension feature bits in the processor feature /* Disable the security extension feature bits in the processor feature
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
*/ */
cpu->id_pfr1 &= ~0xf0; cpu->isar.id_pfr1 &= ~0xf0;
cpu->isar.id_aa64pfr0 &= ~0xf000; cpu->isar.id_aa64pfr0 &= ~0xf000;
} }
@ -1696,7 +1696,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* id_aa64pfr0_el1[11:8]. * id_aa64pfr0_el1[11:8].
*/ */
cpu->isar.id_aa64pfr0 &= ~0xf00; cpu->isar.id_aa64pfr0 &= ~0xf00;
cpu->id_pfr1 &= ~0xf000; cpu->isar.id_pfr1 &= ~0xf000;
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -1894,8 +1894,8 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00011111; cpu->isar.mvfr1 = 0x00011111;
cpu->ctr = 0x82048004; cpu->ctr = 0x82048004;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x1031; cpu->isar.id_pfr0 = 0x1031;
cpu->id_pfr1 = 0x11; cpu->isar.id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x400; cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003; cpu->isar.id_mmfr0 = 0x31100003;
@ -1966,8 +1966,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.mvfr1 = 0x01111111; cpu->isar.mvfr1 = 0x01111111;
cpu->ctr = 0x80038003; cpu->ctr = 0x80038003;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x1031; cpu->isar.id_pfr0 = 0x1031;
cpu->id_pfr1 = 0x11; cpu->isar.id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x000; cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103; cpu->isar.id_mmfr0 = 0x00100103;
@ -2030,8 +2030,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111; cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x84448003; cpu->ctr = 0x84448003;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x00001131; cpu->isar.id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011; cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
@ -2075,8 +2075,8 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111; cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50078; cpu->reset_sctlr = 0x00c50078;
cpu->id_pfr0 = 0x00001131; cpu->isar.id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011; cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x02010555; cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;

4
target/arm/cpu.h
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@ -906,6 +906,8 @@ struct ARMCPU {
uint32_t id_mmfr2; uint32_t id_mmfr2;
uint32_t id_mmfr3; uint32_t id_mmfr3;
uint32_t id_mmfr4; uint32_t id_mmfr4;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t mvfr0; uint32_t mvfr0;
uint32_t mvfr1; uint32_t mvfr1;
uint32_t mvfr2; uint32_t mvfr2;
@ -926,8 +928,6 @@ struct ARMCPU {
uint32_t reset_fpsid; uint32_t reset_fpsid;
uint32_t ctr; uint32_t ctr;
uint32_t reset_sctlr; uint32_t reset_sctlr;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint64_t pmceid0; uint64_t pmceid0;
uint64_t pmceid1; uint64_t pmceid1;
uint32_t id_afr0; uint32_t id_afr0;

12
target/arm/cpu64.c
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@ -108,8 +108,8 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131; cpu->isar.id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011; cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
@ -161,8 +161,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131; cpu->isar.id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011; cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105; cpu->isar.id_mmfr0 = 0x10101105;
@ -213,8 +213,8 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043; cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004; cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838; cpu->reset_sctlr = 0x00c50838;
cpu->id_pfr0 = 0x00000131; cpu->isar.id_pfr0 = 0x00000131;
cpu->id_pfr1 = 0x00011011; cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_dfr0 = 0x03010066; cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105; cpu->isar.id_mmfr0 = 0x10201105;

36
target/arm/cpu_tcg.c
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@ -142,8 +142,8 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111; cpu->isar.id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1; cpu->isar.id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -173,8 +173,8 @@ static void arm1136_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111; cpu->isar.id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1; cpu->isar.id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0x2; cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3; cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -205,8 +205,8 @@ static void arm1176_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2; cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078; cpu->reset_sctlr = 0x00050078;
cpu->id_pfr0 = 0x111; cpu->isar.id_pfr0 = 0x111;
cpu->id_pfr1 = 0x11; cpu->isar.id_pfr1 = 0x11;
cpu->isar.id_dfr0 = 0x33; cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0; cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003; cpu->isar.id_mmfr0 = 0x01130003;
@ -234,8 +234,8 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.mvfr0 = 0x11111111; cpu->isar.mvfr0 = 0x11111111;
cpu->isar.mvfr1 = 0x00000000; cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
cpu->id_pfr0 = 0x111; cpu->isar.id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1; cpu->isar.id_pfr1 = 0x1;
cpu->isar.id_dfr0 = 0; cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2; cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103; cpu->isar.id_mmfr0 = 0x01100103;
@ -266,8 +266,8 @@ static void cortex_m3_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
cpu->midr = 0x410fc231; cpu->midr = 0x410fc231;
cpu->pmsav7_dregion = 8; cpu->pmsav7_dregion = 8;
cpu->id_pfr0 = 0x00000030; cpu->isar.id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200; cpu->isar.id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
@ -296,8 +296,8 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021; cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011; cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000000; cpu->isar.mvfr2 = 0x00000000;
cpu->id_pfr0 = 0x00000030; cpu->isar.id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200; cpu->isar.id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030; cpu->isar.id_mmfr0 = 0x00000030;
@ -326,8 +326,8 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221; cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12000011; cpu->isar.mvfr1 = 0x12000011;
cpu->isar.mvfr2 = 0x00000040; cpu->isar.mvfr2 = 0x00000040;
cpu->id_pfr0 = 0x00000030; cpu->isar.id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000200; cpu->isar.id_pfr1 = 0x00000200;
cpu->isar.id_dfr0 = 0x00100000; cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030; cpu->isar.id_mmfr0 = 0x00100030;
@ -358,8 +358,8 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021; cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011; cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000040; cpu->isar.mvfr2 = 0x00000040;
cpu->id_pfr0 = 0x00000030; cpu->isar.id_pfr0 = 0x00000030;
cpu->id_pfr1 = 0x00000210; cpu->isar.id_pfr1 = 0x00000210;
cpu->isar.id_dfr0 = 0x00200000; cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000; cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40; cpu->isar.id_mmfr0 = 0x00101F40;
@ -397,8 +397,8 @@ static void cortex_r5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMSA);
set_feature(&cpu->env, ARM_FEATURE_PMU); set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->midr = 0x411fc153; /* r1p3 */ cpu->midr = 0x411fc153; /* r1p3 */
cpu->id_pfr0 = 0x0131; cpu->isar.id_pfr0 = 0x0131;
cpu->id_pfr1 = 0x001; cpu->isar.id_pfr1 = 0x001;
cpu->isar.id_dfr0 = 0x010400; cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0; cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030; cpu->isar.id_mmfr0 = 0x0210030;

4
target/arm/helper.c
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@ -6625,7 +6625,7 @@ static void define_pmu_regs(ARMCPU *cpu)
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
uint64_t pfr1 = cpu->id_pfr1; uint64_t pfr1 = cpu->isar.id_pfr1;
if (env->gicv3state) { if (env->gicv3state) {
pfr1 |= 1 << 28; pfr1 |= 1 << 28;
@ -7258,7 +7258,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST, .access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3, .accessfn = access_aa32_tid3,
.resetvalue = cpu->id_pfr0 }, .resetvalue = cpu->isar.id_pfr0 },
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
* the value of the GIC field until after we define these regs. * the value of the GIC field until after we define these regs.
*/ */

4
target/arm/kvm64.c
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@ -555,6 +555,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* than skipping the reads and leaving 0, as we must avoid * than skipping the reads and leaving 0, as we must avoid
* considering the values in every case. * considering the values in every case.
*/ */
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
ARM64_SYS_REG(3, 0, 0, 1, 0));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
ARM64_SYS_REG(3, 0, 0, 1, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2)); ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,