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target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order 

When VSX support was initially added, the fpr registers were added at
offset 0 of the VSR register and the vsrl registers were added at offset
1. This is in contrast to the VMX registers (the last 32 VSX registers) which
are stored in host-endian order.

Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also
stored in host endian order to match the VMX registers. This ensures that TCG
vector operations involving mixed VMX and VSX registers will function
correctly.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Mark Cave-Ayland 2019-03-07 18:05:19 +00:00 committed by David Gibson
parent 37da91f163
commit 8a14d31b00
3 changed files with 10 additions and 10 deletions
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4
target/ppc/cpu.h
View File

@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
static inline int fpr_offset(int i)
{
return offsetof(CPUPPCState, vsr[i].u64[0]);
return offsetof(CPUPPCState, vsr[i].VsrD(0));
}
static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
static inline int vsrl_offset(int i)
{
return offsetof(CPUPPCState, vsr[i].u64[1]);
return offsetof(CPUPPCState, vsr[i].VsrD(1));
}
static inline int vsr_full_offset(int i)

8
target/ppc/internal.h
View File

@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
{
vsr->VsrD(0) = env->vsr[n].u64[0];
vsr->VsrD(1) = env->vsr[n].u64[1];
vsr->VsrD(0) = env->vsr[n].VsrD(0);
vsr->VsrD(1) = env->vsr[n].VsrD(1);
}
static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
{
env->vsr[n].u64[0] = vsr->VsrD(0);
env->vsr[n].u64[1] = vsr->VsrD(1);
env->vsr[n].VsrD(0) = vsr->VsrD(0);
env->vsr[n].VsrD(1) = vsr->VsrD(1);
}
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);

8
target/ppc/machine.c
View File

@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
v->u64[0] = qemu_get_be64(f);
v->VsrD(0) = qemu_get_be64(f);
return 0;
}
@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
qemu_put_be64(f, v->u64[0]);
qemu_put_be64(f, v->VsrD(0));
return 0;
}
@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
v->u64[1] = qemu_get_be64(f);
v->VsrD(1) = qemu_get_be64(f);
return 0;
}
@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size,
{
ppc_vsr_t *v = pv;
qemu_put_be64(f, v->u64[1]);
qemu_put_be64(f, v->VsrD(1));
return 0;
}