emulated nvme updates and fixes
* fixes for Coverity CID 1450756, 1450757 and 1450758 (me) * fix for a bug in zone management receive (me) * metadata and end-to-end data protection support (me & Gollu Appalanaidu) * verify support (Gollu Appalanaidu) * multiple lba formats and format nvm support (Minwoo Im) and a couple of misc refactorings from me. v2: - remove an unintended submodule update. Argh. -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmBTP0wACgkQTeGvMW1P DelZvAf+Ijw77YLz2t0P97CiwoOAG4FADwo61WQJo2AHyS3JMYPVdgNUXF7UGt/S cNhU1JjdEylgZPKi5t9o/qgy7+vtSL0KKqoXIS0z9ZWZkdFsgObNetGULhaqXgaX 4KcAt7PyJS/33uFqYGSVZxJTO4GtCy34hGw6XrVs388tQD1S+eI+oS5EYBN57rl9 MrV5Z72iMCBx8Y074u81SD/u7n34b5WWbUOJADVI1rAKhilDhnkAhBQ/gK/UBodB trUUQY/KU+eCnXEqfBeMD6fL75UOAFOjnm7Kfk/Q/g3di3H2fu0RGLrJuSS1dG0n zmwgE7pQ1jT1UcB3QwAJLR3tGtd6sA== =HwqP -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging emulated nvme updates and fixes * fixes for Coverity CID 1450756, 1450757 and 1450758 (me) * fix for a bug in zone management receive (me) * metadata and end-to-end data protection support (me & Gollu Appalanaidu) * verify support (Gollu Appalanaidu) * multiple lba formats and format nvm support (Minwoo Im) and a couple of misc refactorings from me. v2: - remove an unintended submodule update. Argh. # gpg: Signature made Thu 18 Mar 2021 11:53:48 GMT # gpg: using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9 # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown] # gpg: aka "Klaus Jensen <k.jensen@samsung.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468 4272 63D5 6FC5 E55D A838 # Subkey fingerprint: 5228 33AA 75E2 DCE6 A247 66C0 4DE1 AF31 6D4F 0DE9 * remotes/nvme/tags/nvme-next-pull-request: hw/block/nvme: add support for the format nvm command hw/block/nvme: pull lba format initialization hw/block/nvme: prefer runtime helpers instead of device parameters hw/block/nvme: support multiple lba formats hw/block/nvme: add non-mdts command size limit for verify hw/block/nvme: add verify command hw/block/nvme: end-to-end data protection hw/block/nvme: add metadata support hw/block/nvme: fix zone management receive reporting too many zones hw/block/nvme: assert namespaces array indices hw/block/nvme: fix potential overflow Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
8a40754bca
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|
@ -13,7 +13,7 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
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|||
softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
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softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
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softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c'))
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softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c', 'nvme-subsys.c'))
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softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c', 'nvme-subsys.c', 'nvme-dif.c'))
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specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c'))
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specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk.c'))
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|
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@ -0,0 +1,508 @@
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#include "qemu/osdep.h"
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#include "hw/block/block.h"
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#include "sysemu/dma.h"
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#include "sysemu/block-backend.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "nvme.h"
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#include "nvme-dif.h"
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uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba,
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uint32_t reftag)
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{
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if ((NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) == NVME_ID_NS_DPS_TYPE_1) &&
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(ctrl & NVME_RW_PRINFO_PRCHK_REF) && (slba & 0xffffffff) != reftag) {
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return NVME_INVALID_PROT_INFO | NVME_DNR;
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}
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return NVME_SUCCESS;
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}
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/* from Linux kernel (crypto/crct10dif_common.c) */
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static uint16_t crc_t10dif(uint16_t crc, const unsigned char *buffer,
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size_t len)
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{
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unsigned int i;
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for (i = 0; i < len; i++) {
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crc = (crc << 8) ^ t10_dif_crc_table[((crc >> 8) ^ buffer[i]) & 0xff];
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}
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return crc;
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}
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void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t len,
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uint8_t *mbuf, size_t mlen, uint16_t apptag,
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uint32_t reftag)
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{
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uint8_t *end = buf + len;
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size_t lsize = nvme_lsize(ns);
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size_t msize = nvme_msize(ns);
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int16_t pil = 0;
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = nvme_msize(ns) - sizeof(NvmeDifTuple);
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}
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trace_pci_nvme_dif_pract_generate_dif(len, lsize, lsize + pil, apptag,
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reftag);
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for (; buf < end; buf += lsize, mbuf += msize) {
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NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
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uint16_t crc = crc_t10dif(0x0, buf, lsize);
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if (pil) {
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crc = crc_t10dif(crc, mbuf, pil);
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}
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dif->guard = cpu_to_be16(crc);
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dif->apptag = cpu_to_be16(apptag);
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dif->reftag = cpu_to_be32(reftag);
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if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) != NVME_ID_NS_DPS_TYPE_3) {
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reftag++;
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}
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}
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}
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static uint16_t nvme_dif_prchk(NvmeNamespace *ns, NvmeDifTuple *dif,
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uint8_t *buf, uint8_t *mbuf, size_t pil,
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uint16_t ctrl, uint16_t apptag,
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uint16_t appmask, uint32_t reftag)
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{
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switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
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case NVME_ID_NS_DPS_TYPE_3:
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if (be32_to_cpu(dif->reftag) != 0xffffffff) {
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break;
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||||
}
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||||
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/* fallthrough */
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case NVME_ID_NS_DPS_TYPE_1:
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case NVME_ID_NS_DPS_TYPE_2:
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if (be16_to_cpu(dif->apptag) != 0xffff) {
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break;
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}
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trace_pci_nvme_dif_prchk_disabled(be16_to_cpu(dif->apptag),
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be32_to_cpu(dif->reftag));
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return NVME_SUCCESS;
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}
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if (ctrl & NVME_RW_PRINFO_PRCHK_GUARD) {
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uint16_t crc = crc_t10dif(0x0, buf, nvme_lsize(ns));
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if (pil) {
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crc = crc_t10dif(crc, mbuf, pil);
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}
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trace_pci_nvme_dif_prchk_guard(be16_to_cpu(dif->guard), crc);
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if (be16_to_cpu(dif->guard) != crc) {
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return NVME_E2E_GUARD_ERROR;
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||||
}
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||||
}
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if (ctrl & NVME_RW_PRINFO_PRCHK_APP) {
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trace_pci_nvme_dif_prchk_apptag(be16_to_cpu(dif->apptag), apptag,
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appmask);
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if ((be16_to_cpu(dif->apptag) & appmask) != (apptag & appmask)) {
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return NVME_E2E_APP_ERROR;
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}
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}
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if (ctrl & NVME_RW_PRINFO_PRCHK_REF) {
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trace_pci_nvme_dif_prchk_reftag(be32_to_cpu(dif->reftag), reftag);
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if (be32_to_cpu(dif->reftag) != reftag) {
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return NVME_E2E_REF_ERROR;
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}
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}
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return NVME_SUCCESS;
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}
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uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len,
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uint8_t *mbuf, size_t mlen, uint16_t ctrl,
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uint64_t slba, uint16_t apptag,
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uint16_t appmask, uint32_t reftag)
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{
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uint8_t *end = buf + len;
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size_t lsize = nvme_lsize(ns);
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size_t msize = nvme_msize(ns);
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int16_t pil = 0;
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uint16_t status;
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status = nvme_check_prinfo(ns, ctrl, slba, reftag);
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if (status) {
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return status;
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}
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = nvme_msize(ns) - sizeof(NvmeDifTuple);
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}
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trace_pci_nvme_dif_check(NVME_RW_PRINFO(ctrl), lsize + pil);
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for (; buf < end; buf += lsize, mbuf += msize) {
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NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
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status = nvme_dif_prchk(ns, dif, buf, mbuf, pil, ctrl, apptag,
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appmask, reftag);
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if (status) {
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return status;
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}
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if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) != NVME_ID_NS_DPS_TYPE_3) {
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reftag++;
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}
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}
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return NVME_SUCCESS;
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}
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uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t mlen,
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uint64_t slba)
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{
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BlockBackend *blk = ns->blkconf.blk;
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BlockDriverState *bs = blk_bs(blk);
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size_t msize = nvme_msize(ns);
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size_t lsize = nvme_lsize(ns);
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int64_t moffset = 0, offset = nvme_l2b(ns, slba);
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uint8_t *mbufp, *end;
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bool zeroed;
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int16_t pil = 0;
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int64_t bytes = (mlen / msize) * lsize;
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int64_t pnum = 0;
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Error *err = NULL;
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if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) {
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pil = nvme_msize(ns) - sizeof(NvmeDifTuple);
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}
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do {
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int ret;
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bytes -= pnum;
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ret = bdrv_block_status(bs, offset, bytes, &pnum, NULL, NULL);
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||||
if (ret < 0) {
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error_setg_errno(&err, -ret, "unable to get block status");
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error_report_err(err);
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||||
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return NVME_INTERNAL_DEV_ERROR;
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}
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zeroed = !!(ret & BDRV_BLOCK_ZERO);
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||||
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trace_pci_nvme_block_status(offset, bytes, pnum, ret, zeroed);
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||||
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||||
if (zeroed) {
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||||
mbufp = mbuf + moffset;
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mlen = (pnum / lsize) * msize;
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end = mbufp + mlen;
|
||||
|
||||
for (; mbufp < end; mbufp += msize) {
|
||||
memset(mbufp + pil, 0xff, sizeof(NvmeDifTuple));
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||||
}
|
||||
}
|
||||
|
||||
moffset += (pnum / lsize) * msize;
|
||||
offset += pnum;
|
||||
} while (pnum != bytes);
|
||||
|
||||
return NVME_SUCCESS;
|
||||
}
|
||||
|
||||
static void nvme_dif_rw_cb(void *opaque, int ret)
|
||||
{
|
||||
NvmeBounceContext *ctx = opaque;
|
||||
NvmeRequest *req = ctx->req;
|
||||
NvmeNamespace *ns = req->ns;
|
||||
BlockBackend *blk = ns->blkconf.blk;
|
||||
|
||||
trace_pci_nvme_dif_rw_cb(nvme_cid(req), blk_name(blk));
|
||||
|
||||
qemu_iovec_destroy(&ctx->data.iov);
|
||||
g_free(ctx->data.bounce);
|
||||
|
||||
qemu_iovec_destroy(&ctx->mdata.iov);
|
||||
g_free(ctx->mdata.bounce);
|
||||
|
||||
g_free(ctx);
|
||||
|
||||
nvme_rw_complete_cb(req, ret);
|
||||
}
|
||||
|
||||
static void nvme_dif_rw_check_cb(void *opaque, int ret)
|
||||
{
|
||||
NvmeBounceContext *ctx = opaque;
|
||||
NvmeRequest *req = ctx->req;
|
||||
NvmeNamespace *ns = req->ns;
|
||||
NvmeCtrl *n = nvme_ctrl(req);
|
||||
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
|
||||
uint64_t slba = le64_to_cpu(rw->slba);
|
||||
uint16_t ctrl = le16_to_cpu(rw->control);
|
||||
uint16_t apptag = le16_to_cpu(rw->apptag);
|
||||
uint16_t appmask = le16_to_cpu(rw->appmask);
|
||||
uint32_t reftag = le32_to_cpu(rw->reftag);
|
||||
uint16_t status;
|
||||
|
||||
trace_pci_nvme_dif_rw_check_cb(nvme_cid(req), NVME_RW_PRINFO(ctrl), apptag,
|
||||
appmask, reftag);
|
||||
|
||||
if (ret) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
status = nvme_dif_mangle_mdata(ns, ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
slba);
|
||||
if (status) {
|
||||
req->status = status;
|
||||
goto out;
|
||||
}
|
||||
|
||||
status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
|
||||
ctx->mdata.bounce, ctx->mdata.iov.size, ctrl,
|
||||
slba, apptag, appmask, reftag);
|
||||
if (status) {
|
||||
req->status = status;
|
||||
goto out;
|
||||
}
|
||||
|
||||
status = nvme_bounce_data(n, ctx->data.bounce, ctx->data.iov.size,
|
||||
NVME_TX_DIRECTION_FROM_DEVICE, req);
|
||||
if (status) {
|
||||
req->status = status;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (ctrl & NVME_RW_PRINFO_PRACT && nvme_msize(ns) == 8) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
status = nvme_bounce_mdata(n, ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
NVME_TX_DIRECTION_FROM_DEVICE, req);
|
||||
if (status) {
|
||||
req->status = status;
|
||||
}
|
||||
|
||||
out:
|
||||
nvme_dif_rw_cb(ctx, ret);
|
||||
}
|
||||
|
||||
static void nvme_dif_rw_mdata_in_cb(void *opaque, int ret)
|
||||
{
|
||||
NvmeBounceContext *ctx = opaque;
|
||||
NvmeRequest *req = ctx->req;
|
||||
NvmeNamespace *ns = req->ns;
|
||||
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
|
||||
uint64_t slba = le64_to_cpu(rw->slba);
|
||||
uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
|
||||
size_t mlen = nvme_m2b(ns, nlb);
|
||||
uint64_t offset = ns->mdata_offset + nvme_m2b(ns, slba);
|
||||
BlockBackend *blk = ns->blkconf.blk;
|
||||
|
||||
trace_pci_nvme_dif_rw_mdata_in_cb(nvme_cid(req), blk_name(blk));
|
||||
|
||||
if (ret) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
ctx->mdata.bounce = g_malloc(mlen);
|
||||
|
||||
qemu_iovec_reset(&ctx->mdata.iov);
|
||||
qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
|
||||
|
||||
req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0,
|
||||
nvme_dif_rw_check_cb, ctx);
|
||||
return;
|
||||
|
||||
out:
|
||||
nvme_dif_rw_cb(ctx, ret);
|
||||
}
|
||||
|
||||
static void nvme_dif_rw_mdata_out_cb(void *opaque, int ret)
|
||||
{
|
||||
NvmeBounceContext *ctx = opaque;
|
||||
NvmeRequest *req = ctx->req;
|
||||
NvmeNamespace *ns = req->ns;
|
||||
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
|
||||
uint64_t slba = le64_to_cpu(rw->slba);
|
||||
uint64_t offset = ns->mdata_offset + nvme_m2b(ns, slba);
|
||||
BlockBackend *blk = ns->blkconf.blk;
|
||||
|
||||
trace_pci_nvme_dif_rw_mdata_out_cb(nvme_cid(req), blk_name(blk));
|
||||
|
||||
if (ret) {
|
||||
goto out;
|
||||
}
|
||||
|
||||
req->aiocb = blk_aio_pwritev(blk, offset, &ctx->mdata.iov, 0,
|
||||
nvme_dif_rw_cb, ctx);
|
||||
return;
|
||||
|
||||
out:
|
||||
nvme_dif_rw_cb(ctx, ret);
|
||||
}
|
||||
|
||||
uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req)
|
||||
{
|
||||
NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;
|
||||
NvmeNamespace *ns = req->ns;
|
||||
BlockBackend *blk = ns->blkconf.blk;
|
||||
bool wrz = rw->opcode == NVME_CMD_WRITE_ZEROES;
|
||||
uint32_t nlb = le16_to_cpu(rw->nlb) + 1;
|
||||
uint64_t slba = le64_to_cpu(rw->slba);
|
||||
size_t len = nvme_l2b(ns, nlb);
|
||||
size_t mlen = nvme_m2b(ns, nlb);
|
||||
size_t mapped_len = len;
|
||||
int64_t offset = nvme_l2b(ns, slba);
|
||||
uint16_t ctrl = le16_to_cpu(rw->control);
|
||||
uint16_t apptag = le16_to_cpu(rw->apptag);
|
||||
uint16_t appmask = le16_to_cpu(rw->appmask);
|
||||
uint32_t reftag = le32_to_cpu(rw->reftag);
|
||||
bool pract = !!(ctrl & NVME_RW_PRINFO_PRACT);
|
||||
NvmeBounceContext *ctx;
|
||||
uint16_t status;
|
||||
|
||||
trace_pci_nvme_dif_rw(pract, NVME_RW_PRINFO(ctrl));
|
||||
|
||||
ctx = g_new0(NvmeBounceContext, 1);
|
||||
ctx->req = req;
|
||||
|
||||
if (wrz) {
|
||||
BdrvRequestFlags flags = BDRV_REQ_MAY_UNMAP;
|
||||
|
||||
if (ctrl & NVME_RW_PRINFO_PRCHK_MASK) {
|
||||
status = NVME_INVALID_PROT_INFO | NVME_DNR;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (pract) {
|
||||
uint8_t *mbuf, *end;
|
||||
size_t msize = nvme_msize(ns);
|
||||
int16_t pil = msize - sizeof(NvmeDifTuple);
|
||||
|
||||
status = nvme_check_prinfo(ns, ctrl, slba, reftag);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
flags = 0;
|
||||
|
||||
ctx->mdata.bounce = g_malloc0(mlen);
|
||||
|
||||
qemu_iovec_init(&ctx->mdata.iov, 1);
|
||||
qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
|
||||
|
||||
mbuf = ctx->mdata.bounce;
|
||||
end = mbuf + mlen;
|
||||
|
||||
if (ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT) {
|
||||
pil = 0;
|
||||
}
|
||||
|
||||
for (; mbuf < end; mbuf += msize) {
|
||||
NvmeDifTuple *dif = (NvmeDifTuple *)(mbuf + pil);
|
||||
|
||||
dif->apptag = cpu_to_be16(apptag);
|
||||
dif->reftag = cpu_to_be32(reftag);
|
||||
|
||||
switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) {
|
||||
case NVME_ID_NS_DPS_TYPE_1:
|
||||
case NVME_ID_NS_DPS_TYPE_2:
|
||||
reftag++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
req->aiocb = blk_aio_pwrite_zeroes(blk, offset, len, flags,
|
||||
nvme_dif_rw_mdata_out_cb, ctx);
|
||||
return NVME_NO_COMPLETE;
|
||||
}
|
||||
|
||||
if (nvme_ns_ext(ns) && !(pract && nvme_msize(ns) == 8)) {
|
||||
mapped_len += mlen;
|
||||
}
|
||||
|
||||
status = nvme_map_dptr(n, &req->sg, mapped_len, &req->cmd);
|
||||
if (status) {
|
||||
return status;
|
||||
}
|
||||
|
||||
ctx->data.bounce = g_malloc(len);
|
||||
|
||||
qemu_iovec_init(&ctx->data.iov, 1);
|
||||
qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, len);
|
||||
|
||||
if (req->cmd.opcode == NVME_CMD_READ) {
|
||||
block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size,
|
||||
BLOCK_ACCT_READ);
|
||||
|
||||
req->aiocb = blk_aio_preadv(ns->blkconf.blk, offset, &ctx->data.iov, 0,
|
||||
nvme_dif_rw_mdata_in_cb, ctx);
|
||||
return NVME_NO_COMPLETE;
|
||||
}
|
||||
|
||||
status = nvme_bounce_data(n, ctx->data.bounce, ctx->data.iov.size,
|
||||
NVME_TX_DIRECTION_TO_DEVICE, req);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
ctx->mdata.bounce = g_malloc(mlen);
|
||||
|
||||
qemu_iovec_init(&ctx->mdata.iov, 1);
|
||||
qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen);
|
||||
|
||||
if (!(pract && nvme_msize(ns) == 8)) {
|
||||
status = nvme_bounce_mdata(n, ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
NVME_TX_DIRECTION_TO_DEVICE, req);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
status = nvme_check_prinfo(ns, ctrl, slba, reftag);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (pract) {
|
||||
/* splice generated protection information into the buffer */
|
||||
nvme_dif_pract_generate_dif(ns, ctx->data.bounce, ctx->data.iov.size,
|
||||
ctx->mdata.bounce, ctx->mdata.iov.size,
|
||||
apptag, reftag);
|
||||
} else {
|
||||
status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size,
|
||||
ctx->mdata.bounce, ctx->mdata.iov.size, ctrl,
|
||||
slba, apptag, appmask, reftag);
|
||||
if (status) {
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size,
|
||||
BLOCK_ACCT_WRITE);
|
||||
|
||||
req->aiocb = blk_aio_pwritev(ns->blkconf.blk, offset, &ctx->data.iov, 0,
|
||||
nvme_dif_rw_mdata_out_cb, ctx);
|
||||
|
||||
return NVME_NO_COMPLETE;
|
||||
|
||||
err:
|
||||
qemu_iovec_destroy(&ctx->data.iov);
|
||||
g_free(ctx->data.bounce);
|
||||
|
||||
qemu_iovec_destroy(&ctx->mdata.iov);
|
||||
g_free(ctx->mdata.bounce);
|
||||
|
||||
g_free(ctx);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#ifndef HW_NVME_DIF_H
|
||||
#define HW_NVME_DIF_H
|
||||
|
||||
/* from Linux kernel (crypto/crct10dif_common.c) */
|
||||
static const uint16_t t10_dif_crc_table[256] = {
|
||||
0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B,
|
||||
0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6,
|
||||
0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6,
|
||||
0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B,
|
||||
0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1,
|
||||
0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C,
|
||||
0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C,
|
||||
0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781,
|
||||
0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8,
|
||||
0x373E, 0xBC89, 0xABE7, 0x2050, 0x853B, 0x0E8C, 0x19E2, 0x9255,
|
||||
0x8C4E, 0x07F9, 0x1097, 0x9B20, 0x3E4B, 0xB5FC, 0xA292, 0x2925,
|
||||
0x63F3, 0xE844, 0xFF2A, 0x749D, 0xD1F6, 0x5A41, 0x4D2F, 0xC698,
|
||||
0x7119, 0xFAAE, 0xEDC0, 0x6677, 0xC31C, 0x48AB, 0x5FC5, 0xD472,
|
||||
0x9EA4, 0x1513, 0x027D, 0x89CA, 0x2CA1, 0xA716, 0xB078, 0x3BCF,
|
||||
0x25D4, 0xAE63, 0xB90D, 0x32BA, 0x97D1, 0x1C66, 0x0B08, 0x80BF,
|
||||
0xCA69, 0x41DE, 0x56B0, 0xDD07, 0x786C, 0xF3DB, 0xE4B5, 0x6F02,
|
||||
0x3AB1, 0xB106, 0xA668, 0x2DDF, 0x88B4, 0x0303, 0x146D, 0x9FDA,
|
||||
0xD50C, 0x5EBB, 0x49D5, 0xC262, 0x6709, 0xECBE, 0xFBD0, 0x7067,
|
||||
0x6E7C, 0xE5CB, 0xF2A5, 0x7912, 0xDC79, 0x57CE, 0x40A0, 0xCB17,
|
||||
0x81C1, 0x0A76, 0x1D18, 0x96AF, 0x33C4, 0xB873, 0xAF1D, 0x24AA,
|
||||
0x932B, 0x189C, 0x0FF2, 0x8445, 0x212E, 0xAA99, 0xBDF7, 0x3640,
|
||||
0x7C96, 0xF721, 0xE04F, 0x6BF8, 0xCE93, 0x4524, 0x524A, 0xD9FD,
|
||||
0xC7E6, 0x4C51, 0x5B3F, 0xD088, 0x75E3, 0xFE54, 0xE93A, 0x628D,
|
||||
0x285B, 0xA3EC, 0xB482, 0x3F35, 0x9A5E, 0x11E9, 0x0687, 0x8D30,
|
||||
0xE232, 0x6985, 0x7EEB, 0xF55C, 0x5037, 0xDB80, 0xCCEE, 0x4759,
|
||||
0x0D8F, 0x8638, 0x9156, 0x1AE1, 0xBF8A, 0x343D, 0x2353, 0xA8E4,
|
||||
0xB6FF, 0x3D48, 0x2A26, 0xA191, 0x04FA, 0x8F4D, 0x9823, 0x1394,
|
||||
0x5942, 0xD2F5, 0xC59B, 0x4E2C, 0xEB47, 0x60F0, 0x779E, 0xFC29,
|
||||
0x4BA8, 0xC01F, 0xD771, 0x5CC6, 0xF9AD, 0x721A, 0x6574, 0xEEC3,
|
||||
0xA415, 0x2FA2, 0x38CC, 0xB37B, 0x1610, 0x9DA7, 0x8AC9, 0x017E,
|
||||
0x1F65, 0x94D2, 0x83BC, 0x080B, 0xAD60, 0x26D7, 0x31B9, 0xBA0E,
|
||||
0xF0D8, 0x7B6F, 0x6C01, 0xE7B6, 0x42DD, 0xC96A, 0xDE04, 0x55B3
|
||||
};
|
||||
|
||||
uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba,
|
||||
uint32_t reftag);
|
||||
uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t mlen,
|
||||
uint64_t slba);
|
||||
void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t len,
|
||||
uint8_t *mbuf, size_t mlen, uint16_t apptag,
|
||||
uint32_t reftag);
|
||||
uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len,
|
||||
uint8_t *mbuf, size_t mlen, uint16_t ctrl,
|
||||
uint64_t slba, uint16_t apptag,
|
||||
uint16_t appmask, uint32_t reftag);
|
||||
uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req);
|
||||
|
||||
#endif /* HW_NVME_DIF_H */
|
||||
|
|
@ -32,36 +32,46 @@
|
|||
|
||||
#define MIN_DISCARD_GRANULARITY (4 * KiB)
|
||||
|
||||
static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
|
||||
void nvme_ns_init_format(NvmeNamespace *ns)
|
||||
{
|
||||
BlockDriverInfo bdi;
|
||||
NvmeIdNs *id_ns = &ns->id_ns;
|
||||
int lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
|
||||
int npdg;
|
||||
BlockDriverInfo bdi;
|
||||
int npdg, nlbas, ret;
|
||||
|
||||
ns->id_ns.dlfeat = 0x9;
|
||||
nlbas = nvme_ns_nlbas(ns);
|
||||
|
||||
id_ns->lbaf[lba_index].ds = 31 - clz32(ns->blkconf.logical_block_size);
|
||||
|
||||
id_ns->nsze = cpu_to_le64(nvme_ns_nlbas(ns));
|
||||
|
||||
ns->csi = NVME_CSI_NVM;
|
||||
id_ns->nsze = cpu_to_le64(nlbas);
|
||||
|
||||
/* no thin provisioning */
|
||||
id_ns->ncap = id_ns->nsze;
|
||||
id_ns->nuse = id_ns->ncap;
|
||||
|
||||
/* support DULBE and I/O optimization fields */
|
||||
id_ns->nsfeat |= (0x4 | 0x10);
|
||||
ns->mdata_offset = nvme_l2b(ns, nlbas);
|
||||
|
||||
npdg = ns->blkconf.discard_granularity / ns->blkconf.logical_block_size;
|
||||
npdg = ns->blkconf.discard_granularity / nvme_lsize(ns);
|
||||
|
||||
if (bdrv_get_info(blk_bs(ns->blkconf.blk), &bdi) >= 0 &&
|
||||
bdi.cluster_size > ns->blkconf.discard_granularity) {
|
||||
npdg = bdi.cluster_size / ns->blkconf.logical_block_size;
|
||||
ret = bdrv_get_info(blk_bs(ns->blkconf.blk), &bdi);
|
||||
if (ret >= 0 && bdi.cluster_size > ns->blkconf.discard_granularity) {
|
||||
npdg = bdi.cluster_size / nvme_lsize(ns);
|
||||
}
|
||||
|
||||
id_ns->npda = id_ns->npdg = npdg - 1;
|
||||
}
|
||||
|
||||
static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
|
||||
{
|
||||
NvmeIdNs *id_ns = &ns->id_ns;
|
||||
uint8_t ds;
|
||||
uint16_t ms;
|
||||
int i;
|
||||
|
||||
ns->csi = NVME_CSI_NVM;
|
||||
ns->status = 0x0;
|
||||
|
||||
ns->id_ns.dlfeat = 0x1;
|
||||
|
||||
/* support DULBE and I/O optimization fields */
|
||||
id_ns->nsfeat |= (0x4 | 0x10);
|
||||
|
||||
if (nvme_ns_shared(ns)) {
|
||||
id_ns->nmic |= NVME_NMIC_NS_SHARED;
|
||||
|
|
@ -72,6 +82,61 @@ static int nvme_ns_init(NvmeNamespace *ns, Error **errp)
|
|||
id_ns->mcl = cpu_to_le32(ns->params.mcl);
|
||||
id_ns->msrc = ns->params.msrc;
|
||||
|
||||
ds = 31 - clz32(ns->blkconf.logical_block_size);
|
||||
ms = ns->params.ms;
|
||||
|
||||
if (ns->params.ms) {
|
||||
id_ns->mc = 0x3;
|
||||
|
||||
if (ns->params.mset) {
|
||||
id_ns->flbas |= 0x10;
|
||||
}
|
||||
|
||||
id_ns->dpc = 0x1f;
|
||||
id_ns->dps = ((ns->params.pil & 0x1) << 3) | ns->params.pi;
|
||||
|
||||
NvmeLBAF lbaf[16] = {
|
||||
[0] = { .ds = 9 },
|
||||
[1] = { .ds = 9, .ms = 8 },
|
||||
[2] = { .ds = 9, .ms = 16 },
|
||||
[3] = { .ds = 9, .ms = 64 },
|
||||
[4] = { .ds = 12 },
|
||||
[5] = { .ds = 12, .ms = 8 },
|
||||
[6] = { .ds = 12, .ms = 16 },
|
||||
[7] = { .ds = 12, .ms = 64 },
|
||||
};
|
||||
|
||||
memcpy(&id_ns->lbaf, &lbaf, sizeof(lbaf));
|
||||
id_ns->nlbaf = 7;
|
||||
} else {
|
||||
NvmeLBAF lbaf[16] = {
|
||||
[0] = { .ds = 9 },
|
||||
[1] = { .ds = 12 },
|
||||
};
|
||||
|
||||
memcpy(&id_ns->lbaf, &lbaf, sizeof(lbaf));
|
||||
id_ns->nlbaf = 1;
|
||||
}
|
||||
|
||||
for (i = 0; i <= id_ns->nlbaf; i++) {
|
||||
NvmeLBAF *lbaf = &id_ns->lbaf[i];
|
||||
if (lbaf->ds == ds) {
|
||||
if (lbaf->ms == ms) {
|
||||
id_ns->flbas |= i;
|
||||
goto lbaf_found;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* add non-standard lba format */
|
||||
id_ns->nlbaf++;
|
||||
id_ns->lbaf[id_ns->nlbaf].ds = ds;
|
||||
id_ns->lbaf[id_ns->nlbaf].ms = ms;
|
||||
id_ns->flbas |= id_ns->nlbaf;
|
||||
|
||||
lbaf_found:
|
||||
nvme_ns_init_format(ns);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -105,7 +170,7 @@ static int nvme_ns_init_blk(NvmeNamespace *ns, Error **errp)
|
|||
static int nvme_ns_zoned_check_calc_geometry(NvmeNamespace *ns, Error **errp)
|
||||
{
|
||||
uint64_t zone_size, zone_cap;
|
||||
uint32_t lbasz = ns->blkconf.logical_block_size;
|
||||
uint32_t lbasz = nvme_lsize(ns);
|
||||
|
||||
/* Make sure that the values of ZNS properties are sane */
|
||||
if (ns->params.zone_size_bs) {
|
||||
|
|
@ -140,7 +205,7 @@ static int nvme_ns_zoned_check_calc_geometry(NvmeNamespace *ns, Error **errp)
|
|||
*/
|
||||
ns->zone_size = zone_size / lbasz;
|
||||
ns->zone_capacity = zone_cap / lbasz;
|
||||
ns->num_zones = ns->size / lbasz / ns->zone_size;
|
||||
ns->num_zones = nvme_ns_nlbas(ns) / ns->zone_size;
|
||||
|
||||
/* Do a few more sanity checks of ZNS properties */
|
||||
if (!ns->num_zones) {
|
||||
|
|
@ -229,9 +294,10 @@ static void nvme_ns_zoned_init_state(NvmeNamespace *ns)
|
|||
}
|
||||
}
|
||||
|
||||
static void nvme_ns_init_zoned(NvmeNamespace *ns, int lba_index)
|
||||
static void nvme_ns_init_zoned(NvmeNamespace *ns)
|
||||
{
|
||||
NvmeIdNsZoned *id_ns_z;
|
||||
int i;
|
||||
|
||||
nvme_ns_zoned_init_state(ns);
|
||||
|
||||
|
|
@ -243,9 +309,11 @@ static void nvme_ns_init_zoned(NvmeNamespace *ns, int lba_index)
|
|||
id_ns_z->zoc = 0;
|
||||
id_ns_z->ozcs = ns->params.cross_zone_read ? 0x01 : 0x00;
|
||||
|
||||
id_ns_z->lbafe[lba_index].zsze = cpu_to_le64(ns->zone_size);
|
||||
id_ns_z->lbafe[lba_index].zdes =
|
||||
ns->params.zd_extension_size >> 6; /* Units of 64B */
|
||||
for (i = 0; i <= ns->id_ns.nlbaf; i++) {
|
||||
id_ns_z->lbafe[i].zsze = cpu_to_le64(ns->zone_size);
|
||||
id_ns_z->lbafe[i].zdes =
|
||||
ns->params.zd_extension_size >> 6; /* Units of 64B */
|
||||
}
|
||||
|
||||
ns->csi = NVME_CSI_ZONED;
|
||||
ns->id_ns.nsze = cpu_to_le64(ns->num_zones * ns->zone_size);
|
||||
|
|
@ -326,6 +394,12 @@ static int nvme_ns_check_constraints(NvmeNamespace *ns, Error **errp)
|
|||
return -1;
|
||||
}
|
||||
|
||||
if (ns->params.pi && !ns->params.ms) {
|
||||
error_setg(errp, "at least 8 bytes of metadata required to enable "
|
||||
"protection information");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -346,7 +420,7 @@ int nvme_ns_setup(NvmeNamespace *ns, Error **errp)
|
|||
if (nvme_ns_zoned_check_calc_geometry(ns, errp) != 0) {
|
||||
return -1;
|
||||
}
|
||||
nvme_ns_init_zoned(ns, 0);
|
||||
nvme_ns_init_zoned(ns);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -402,6 +476,10 @@ static Property nvme_ns_props[] = {
|
|||
DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false),
|
||||
DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
|
||||
DEFINE_PROP_UUID("uuid", NvmeNamespace, params.uuid),
|
||||
DEFINE_PROP_UINT16("ms", NvmeNamespace, params.ms, 0),
|
||||
DEFINE_PROP_UINT8("mset", NvmeNamespace, params.mset, 0),
|
||||
DEFINE_PROP_UINT8("pi", NvmeNamespace, params.pi, 0),
|
||||
DEFINE_PROP_UINT8("pil", NvmeNamespace, params.pil, 0),
|
||||
DEFINE_PROP_UINT16("mssrl", NvmeNamespace, params.mssrl, 128),
|
||||
DEFINE_PROP_UINT32("mcl", NvmeNamespace, params.mcl, 128),
|
||||
DEFINE_PROP_UINT8("msrc", NvmeNamespace, params.msrc, 127),
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef NVME_NS_H
|
||||
#define NVME_NS_H
|
||||
|
||||
#include "qemu/uuid.h"
|
||||
|
||||
#define TYPE_NVME_NS "nvme-ns"
|
||||
#define NVME_NS(obj) \
|
||||
OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS)
|
||||
|
|
@ -30,6 +32,11 @@ typedef struct NvmeNamespaceParams {
|
|||
uint32_t nsid;
|
||||
QemuUUID uuid;
|
||||
|
||||
uint16_t ms;
|
||||
uint8_t mset;
|
||||
uint8_t pi;
|
||||
uint8_t pil;
|
||||
|
||||
uint16_t mssrl;
|
||||
uint32_t mcl;
|
||||
uint8_t msrc;
|
||||
|
|
@ -48,9 +55,11 @@ typedef struct NvmeNamespace {
|
|||
BlockConf blkconf;
|
||||
int32_t bootindex;
|
||||
int64_t size;
|
||||
int64_t mdata_offset;
|
||||
NvmeIdNs id_ns;
|
||||
const uint32_t *iocs;
|
||||
uint8_t csi;
|
||||
uint16_t status;
|
||||
|
||||
NvmeSubsystem *subsys;
|
||||
QTAILQ_ENTRY(NvmeNamespace) entry;
|
||||
|
|
@ -76,6 +85,11 @@ typedef struct NvmeNamespace {
|
|||
} features;
|
||||
} NvmeNamespace;
|
||||
|
||||
static inline uint16_t nvme_ns_status(NvmeNamespace *ns)
|
||||
{
|
||||
return ns->status;
|
||||
}
|
||||
|
||||
static inline uint32_t nvme_nsid(NvmeNamespace *ns)
|
||||
{
|
||||
if (ns) {
|
||||
|
|
@ -101,18 +115,41 @@ static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns)
|
|||
return nvme_ns_lbaf(ns)->ds;
|
||||
}
|
||||
|
||||
/* calculate the number of LBAs that the namespace can accomodate */
|
||||
static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns)
|
||||
{
|
||||
return ns->size >> nvme_ns_lbads(ns);
|
||||
}
|
||||
|
||||
/* convert an LBA to the equivalent in bytes */
|
||||
static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba)
|
||||
{
|
||||
return lba << nvme_ns_lbads(ns);
|
||||
}
|
||||
|
||||
static inline size_t nvme_lsize(NvmeNamespace *ns)
|
||||
{
|
||||
return 1 << nvme_ns_lbads(ns);
|
||||
}
|
||||
|
||||
static inline uint16_t nvme_msize(NvmeNamespace *ns)
|
||||
{
|
||||
return nvme_ns_lbaf(ns)->ms;
|
||||
}
|
||||
|
||||
static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba)
|
||||
{
|
||||
return nvme_msize(ns) * lba;
|
||||
}
|
||||
|
||||
static inline bool nvme_ns_ext(NvmeNamespace *ns)
|
||||
{
|
||||
return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas);
|
||||
}
|
||||
|
||||
/* calculate the number of LBAs that the namespace can accomodate */
|
||||
static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns)
|
||||
{
|
||||
if (nvme_msize(ns)) {
|
||||
return ns->size / (nvme_lsize(ns) + nvme_msize(ns));
|
||||
}
|
||||
return ns->size >> nvme_ns_lbads(ns);
|
||||
}
|
||||
|
||||
typedef struct NvmeCtrl NvmeCtrl;
|
||||
|
||||
static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone)
|
||||
|
|
@ -187,6 +224,7 @@ static inline void nvme_aor_dec_active(NvmeNamespace *ns)
|
|||
assert(ns->nr_active_zones >= 0);
|
||||
}
|
||||
|
||||
void nvme_ns_init_format(NvmeNamespace *ns);
|
||||
int nvme_ns_setup(NvmeNamespace *ns, Error **errp);
|
||||
void nvme_ns_drain(NvmeNamespace *ns);
|
||||
void nvme_ns_shutdown(NvmeNamespace *ns);
|
||||
|
|
|
|||
|
|
@ -47,15 +47,18 @@ int nvme_subsys_register_ns(NvmeNamespace *ns, Error **errp)
|
|||
{
|
||||
NvmeSubsystem *subsys = ns->subsys;
|
||||
NvmeCtrl *n;
|
||||
uint32_t nsid = nvme_nsid(ns);
|
||||
int i;
|
||||
|
||||
if (subsys->namespaces[nvme_nsid(ns)]) {
|
||||
assert(nsid && nsid <= NVME_SUBSYS_MAX_NAMESPACES);
|
||||
|
||||
if (subsys->namespaces[nsid]) {
|
||||
error_setg(errp, "namespace %d already registerd to subsy %s",
|
||||
nvme_nsid(ns), subsys->parent_obj.id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
subsys->namespaces[nvme_nsid(ns)] = ns;
|
||||
subsys->namespaces[nsid] = ns;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(subsys->ctrls); i++) {
|
||||
n = subsys->ctrls[i];
|
||||
|
|
|
|||
|
|
@ -54,6 +54,8 @@ static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
assert(nsid && nsid <= NVME_SUBSYS_MAX_NAMESPACES);
|
||||
|
||||
return subsys->namespaces[nsid];
|
||||
}
|
||||
|
||||
|
|
|
|||
1257
hw/block/nvme.c
1257
hw/block/nvme.c
File diff suppressed because it is too large
Load Diff
|
|
@ -2,6 +2,7 @@
|
|||
#define HW_NVME_H
|
||||
|
||||
#include "block/nvme.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "nvme-subsys.h"
|
||||
#include "nvme-ns.h"
|
||||
|
||||
|
|
@ -25,6 +26,7 @@ typedef struct NvmeParams {
|
|||
uint8_t aerl;
|
||||
uint32_t aer_max_queued;
|
||||
uint8_t mdts;
|
||||
uint8_t vsl;
|
||||
bool use_intel_id;
|
||||
uint8_t zasl;
|
||||
bool legacy_cmb;
|
||||
|
|
@ -62,6 +64,15 @@ typedef struct NvmeRequest {
|
|||
QTAILQ_ENTRY(NvmeRequest)entry;
|
||||
} NvmeRequest;
|
||||
|
||||
typedef struct NvmeBounceContext {
|
||||
NvmeRequest *req;
|
||||
|
||||
struct {
|
||||
QEMUIOVector iov;
|
||||
uint8_t *bounce;
|
||||
} data, mdata;
|
||||
} NvmeBounceContext;
|
||||
|
||||
static inline const char *nvme_adm_opc_str(uint8_t opc)
|
||||
{
|
||||
switch (opc) {
|
||||
|
|
@ -75,6 +86,7 @@ static inline const char *nvme_adm_opc_str(uint8_t opc)
|
|||
case NVME_ADM_CMD_SET_FEATURES: return "NVME_ADM_CMD_SET_FEATURES";
|
||||
case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
|
||||
case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
|
||||
case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
|
||||
default: return "NVME_ADM_CMD_UNKNOWN";
|
||||
}
|
||||
}
|
||||
|
|
@ -88,6 +100,7 @@ static inline const char *nvme_io_opc_str(uint8_t opc)
|
|||
case NVME_CMD_COMPARE: return "NVME_NVM_CMD_COMPARE";
|
||||
case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES";
|
||||
case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM";
|
||||
case NVME_CMD_VERIFY: return "NVME_NVM_CMD_VERIFY";
|
||||
case NVME_CMD_COPY: return "NVME_NVM_CMD_COPY";
|
||||
case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_MGMT_SEND";
|
||||
case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_MGMT_RECV";
|
||||
|
|
@ -236,12 +249,18 @@ static inline bool nvme_ns_is_attached(NvmeCtrl *n, NvmeNamespace *ns)
|
|||
|
||||
static inline void nvme_ns_attach(NvmeCtrl *n, NvmeNamespace *ns)
|
||||
{
|
||||
n->namespaces[nvme_nsid(ns) - 1] = ns;
|
||||
uint32_t nsid = nvme_nsid(ns);
|
||||
assert(nsid && nsid <= NVME_MAX_NAMESPACES);
|
||||
|
||||
n->namespaces[nsid - 1] = ns;
|
||||
}
|
||||
|
||||
static inline void nvme_ns_detach(NvmeCtrl *n, NvmeNamespace *ns)
|
||||
{
|
||||
n->namespaces[nvme_nsid(ns) - 1] = NULL;
|
||||
uint32_t nsid = nvme_nsid(ns);
|
||||
assert(nsid && nsid <= NVME_MAX_NAMESPACES);
|
||||
|
||||
n->namespaces[nsid - 1] = NULL;
|
||||
}
|
||||
|
||||
static inline NvmeCQueue *nvme_cq(NvmeRequest *req)
|
||||
|
|
@ -258,6 +277,27 @@ static inline NvmeCtrl *nvme_ctrl(NvmeRequest *req)
|
|||
return sq->ctrl;
|
||||
}
|
||||
|
||||
static inline uint16_t nvme_cid(NvmeRequest *req)
|
||||
{
|
||||
if (!req) {
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
return le16_to_cpu(req->cqe.cid);
|
||||
}
|
||||
|
||||
typedef enum NvmeTxDirection {
|
||||
NVME_TX_DIRECTION_TO_DEVICE = 0,
|
||||
NVME_TX_DIRECTION_FROM_DEVICE = 1,
|
||||
} NvmeTxDirection;
|
||||
|
||||
int nvme_register_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **errp);
|
||||
uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
|
||||
NvmeTxDirection dir, NvmeRequest *req);
|
||||
uint16_t nvme_bounce_mdata(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
|
||||
NvmeTxDirection dir, NvmeRequest *req);
|
||||
void nvme_rw_complete_cb(void *opaque, int ret);
|
||||
uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len,
|
||||
NvmeCmd *cmd);
|
||||
|
||||
#endif /* HW_NVME_H */
|
||||
|
|
|
|||
|
|
@ -41,19 +41,39 @@ pci_nvme_map_sgl(uint8_t typ, uint64_t len) "type 0x%"PRIx8" len %"PRIu64""
|
|||
pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
|
||||
pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
|
||||
pci_nvme_flush(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32""
|
||||
pci_nvme_format(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset, uint8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset %"PRIu8" pi %"PRIu8" pil %"PRIu8""
|
||||
pci_nvme_format_ns(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset, uint8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset %"PRIu8" pi %"PRIu8" pil %"PRIu8""
|
||||
pci_nvme_format_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32""
|
||||
pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
|
||||
pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
|
||||
pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_misc_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_dif_rw(uint8_t pract, uint8_t prinfo) "pract 0x%"PRIx8" prinfo 0x%"PRIx8""
|
||||
pci_nvme_dif_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_dif_rw_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_dif_rw_mdata_out_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_dif_rw_check_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32""
|
||||
pci_nvme_dif_pract_generate_dif(size_t len, size_t lba_size, size_t chksum_len, uint16_t apptag, uint32_t reftag) "len %zu lba_size %zu chksum_len %zu apptag 0x%"PRIx16" reftag 0x%"PRIx32""
|
||||
pci_nvme_dif_check(uint8_t prinfo, uint16_t chksum_len) "prinfo 0x%"PRIx8" chksum_len %"PRIu16""
|
||||
pci_nvme_dif_prchk_disabled(uint16_t apptag, uint32_t reftag) "apptag 0x%"PRIx16" reftag 0x%"PRIx32""
|
||||
pci_nvme_dif_prchk_guard(uint16_t guard, uint16_t crc) "guard 0x%"PRIx16" crc 0x%"PRIx16""
|
||||
pci_nvme_dif_prchk_apptag(uint16_t apptag, uint16_t elbat, uint16_t elbatm) "apptag 0x%"PRIx16" elbat 0x%"PRIx16" elbatm 0x%"PRIx16""
|
||||
pci_nvme_dif_prchk_reftag(uint32_t reftag, uint32_t elbrt) "reftag 0x%"PRIx32" elbrt 0x%"PRIx32""
|
||||
pci_nvme_copy(uint16_t cid, uint32_t nsid, uint16_t nr, uint8_t format) "cid %"PRIu16" nsid %"PRIu32" nr %"PRIu16" format 0x%"PRIx8""
|
||||
pci_nvme_copy_source_range(uint64_t slba, uint32_t nlb) "slba 0x%"PRIx64" nlb %"PRIu32""
|
||||
pci_nvme_copy_in_complete(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_copy_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_verify(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32""
|
||||
pci_nvme_verify_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_verify_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32""
|
||||
pci_nvme_rw_complete_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
|
||||
pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret, bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x zeroed %d"
|
||||
pci_nvme_dsm(uint16_t cid, uint32_t nsid, uint32_t nr, uint32_t attr) "cid %"PRIu16" nsid %"PRIu32" nr %"PRIu32" attr 0x%"PRIx32""
|
||||
pci_nvme_dsm_deallocate(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32""
|
||||
pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl) "nlb %"PRIu32" dmrsl %"PRIu32""
|
||||
pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32""
|
||||
pci_nvme_compare_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_compare_data_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_compare_mdata_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_aio_copy_in_cb(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_aio_zone_reset_cb(uint16_t cid, uint64_t zslba) "cid %"PRIu16" zslba 0x%"PRIx64""
|
||||
|
|
|
|||
|
|
@ -580,6 +580,7 @@ enum NvmeIoCommands {
|
|||
NVME_CMD_COMPARE = 0x05,
|
||||
NVME_CMD_WRITE_ZEROES = 0x08,
|
||||
NVME_CMD_DSM = 0x09,
|
||||
NVME_CMD_VERIFY = 0x0c,
|
||||
NVME_CMD_COPY = 0x19,
|
||||
NVME_CMD_ZONE_MGMT_SEND = 0x79,
|
||||
NVME_CMD_ZONE_MGMT_RECV = 0x7a,
|
||||
|
|
@ -696,12 +697,17 @@ enum {
|
|||
NVME_RW_DSM_LATENCY_LOW = 3 << 4,
|
||||
NVME_RW_DSM_SEQ_REQ = 1 << 6,
|
||||
NVME_RW_DSM_COMPRESSED = 1 << 7,
|
||||
NVME_RW_PIREMAP = 1 << 9,
|
||||
NVME_RW_PRINFO_PRACT = 1 << 13,
|
||||
NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
|
||||
NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
|
||||
NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
|
||||
NVME_RW_PRINFO_PRCHK_MASK = 7 << 10,
|
||||
|
||||
};
|
||||
|
||||
#define NVME_RW_PRINFO(control) ((control >> 10) & 0xf)
|
||||
|
||||
typedef struct QEMU_PACKED NvmeDsmCmd {
|
||||
uint8_t opcode;
|
||||
uint8_t flags;
|
||||
|
|
@ -822,6 +828,7 @@ enum NvmeStatusCodes {
|
|||
NVME_CAP_EXCEEDED = 0x0081,
|
||||
NVME_NS_NOT_READY = 0x0082,
|
||||
NVME_NS_RESV_CONFLICT = 0x0083,
|
||||
NVME_FORMAT_IN_PROGRESS = 0x0084,
|
||||
NVME_INVALID_CQID = 0x0100,
|
||||
NVME_INVALID_QID = 0x0101,
|
||||
NVME_MAX_QSIZE_EXCEEDED = 0x0102,
|
||||
|
|
@ -1079,6 +1086,7 @@ enum NvmeIdCtrlOncs {
|
|||
NVME_ONCS_FEATURES = 1 << 4,
|
||||
NVME_ONCS_RESRVATIONS = 1 << 5,
|
||||
NVME_ONCS_TIMESTAMP = 1 << 6,
|
||||
NVME_ONCS_VERIFY = 1 << 7,
|
||||
NVME_ONCS_COPY = 1 << 8,
|
||||
};
|
||||
|
||||
|
|
@ -1324,14 +1332,22 @@ typedef struct QEMU_PACKED NvmeIdNsZoned {
|
|||
#define NVME_ID_NS_DPC_TYPE_MASK 0x7
|
||||
|
||||
enum NvmeIdNsDps {
|
||||
DPS_TYPE_NONE = 0,
|
||||
DPS_TYPE_1 = 1,
|
||||
DPS_TYPE_2 = 2,
|
||||
DPS_TYPE_3 = 3,
|
||||
DPS_TYPE_MASK = 0x7,
|
||||
DPS_FIRST_EIGHT = 8,
|
||||
NVME_ID_NS_DPS_TYPE_NONE = 0,
|
||||
NVME_ID_NS_DPS_TYPE_1 = 1,
|
||||
NVME_ID_NS_DPS_TYPE_2 = 2,
|
||||
NVME_ID_NS_DPS_TYPE_3 = 3,
|
||||
NVME_ID_NS_DPS_TYPE_MASK = 0x7,
|
||||
NVME_ID_NS_DPS_FIRST_EIGHT = 8,
|
||||
};
|
||||
|
||||
#define NVME_ID_NS_DPS_TYPE(dps) (dps & NVME_ID_NS_DPS_TYPE_MASK)
|
||||
|
||||
typedef struct NvmeDifTuple {
|
||||
uint16_t guard;
|
||||
uint16_t apptag;
|
||||
uint32_t reftag;
|
||||
} NvmeDifTuple;
|
||||
|
||||
enum NvmeZoneAttr {
|
||||
NVME_ZA_FINISHED_BY_CTLR = 1 << 0,
|
||||
NVME_ZA_FINISH_RECOMMENDED = 1 << 1,
|
||||
|
|
@ -1428,5 +1444,6 @@ static inline void _nvme_check_size(void)
|
|||
QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
|
||||
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
|
||||
QEMU_BUILD_BUG_ON(sizeof(NvmeZoneDescr) != 64);
|
||||
QEMU_BUILD_BUG_ON(sizeof(NvmeDifTuple) != 8);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue