OpenE2K/qemu-e2k
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Restore consistent formatting

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Signed-off-by: malc <av1474@comtv.ru>
This commit is contained in:
malc 2011-10-09 19:04:16 +04:00
parent df2921d326
commit 8acbc9b21d
3 changed files with 14 additions and 15 deletions
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10
hw/cs4231a.c
View File

@ -346,7 +346,7 @@ static void cs_reset_voices (CSState *s, uint32_t val)
} }
} }
static uint64_t cs_read(void *opaque, target_phys_addr_t addr, unsigned size) static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
{ {
CSState *s = opaque; CSState *s = opaque;
uint32_t saddr, iaddr, ret; uint32_t saddr, iaddr, ret;
@ -383,8 +383,8 @@ static uint64_t cs_read(void *opaque, target_phys_addr_t addr, unsigned size)
return ret; return ret;
} }
static void cs_write(void *opaque, target_phys_addr_t addr, static void cs_write (void *opaque, target_phys_addr_t addr,
uint64_t val64, unsigned size) uint64_t val64, unsigned size)
{ {
CSState *s = opaque; CSState *s = opaque;
uint32_t saddr, iaddr, val; uint32_t saddr, iaddr, val;
@ -647,8 +647,8 @@ static int cs4231a_initfn (ISADevice *dev)
isa_init_irq (dev, &s->pic, s->irq); isa_init_irq (dev, &s->pic, s->irq);
memory_region_init_io(&s->ioports, &cs_ioport_ops, s, "cs4231a", 4); memory_region_init_io (&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
isa_register_ioport(dev, &s->ioports, s->port); isa_register_ioport (dev, &s->ioports, s->port);
DMA_register_channel (s->dma, cs_dma_read, s); DMA_register_channel (s->dma, cs_dma_read, s);

11
hw/gus.c
View File

@ -234,7 +234,7 @@ static const VMStateDescription vmstate_gus = {
static int gus_initfn (ISADevice *dev) static int gus_initfn (ISADevice *dev)
{ {
GUSState *s = DO_UPCAST(GUSState, dev, dev); GUSState *s = DO_UPCAST (GUSState, dev, dev);
struct audsettings as; struct audsettings as;
AUD_register_card ("gus", &s->card); AUD_register_card ("gus", &s->card);
@ -264,24 +264,23 @@ static int gus_initfn (ISADevice *dev)
register_ioport_write (s->port, 1, 1, gus_writeb, s); register_ioport_write (s->port, 1, 1, gus_writeb, s);
register_ioport_write (s->port, 1, 2, gus_writew, s); register_ioport_write (s->port, 1, 2, gus_writew, s);
isa_init_ioport_range(dev, s->port, 2); isa_init_ioport_range (dev, s->port, 2);
register_ioport_read ((s->port + 0x100) & 0xf00, 1, 1, gus_readb, s); register_ioport_read ((s->port + 0x100) & 0xf00, 1, 1, gus_readb, s);
register_ioport_read ((s->port + 0x100) & 0xf00, 1, 2, gus_readw, s); register_ioport_read ((s->port + 0x100) & 0xf00, 1, 2, gus_readw, s);
isa_init_ioport_range(dev, (s->port + 0x100) & 0xf00, 2); isa_init_ioport_range (dev, (s->port + 0x100) & 0xf00, 2);
register_ioport_write (s->port + 6, 10, 1, gus_writeb, s); register_ioport_write (s->port + 6, 10, 1, gus_writeb, s);
register_ioport_write (s->port + 6, 10, 2, gus_writew, s); register_ioport_write (s->port + 6, 10, 2, gus_writew, s);
register_ioport_read (s->port + 6, 10, 1, gus_readb, s); register_ioport_read (s->port + 6, 10, 1, gus_readb, s);
register_ioport_read (s->port + 6, 10, 2, gus_readw, s); register_ioport_read (s->port + 6, 10, 2, gus_readw, s);
isa_init_ioport_range(dev, s->port + 6, 10); isa_init_ioport_range (dev, s->port + 6, 10);
register_ioport_write (s->port + 0x100, 8, 1, gus_writeb, s); register_ioport_write (s->port + 0x100, 8, 1, gus_writeb, s);
register_ioport_write (s->port + 0x100, 8, 2, gus_writew, s); register_ioport_write (s->port + 0x100, 8, 2, gus_writew, s);
register_ioport_read (s->port + 0x100, 8, 1, gus_readb, s); register_ioport_read (s->port + 0x100, 8, 1, gus_readb, s);
register_ioport_read (s->port + 0x100, 8, 2, gus_readw, s); register_ioport_read (s->port + 0x100, 8, 2, gus_readw, s);
isa_init_ioport_range(dev, s->port + 0x100, 8); isa_init_ioport_range (dev, s->port + 0x100, 8);
DMA_register_channel (s->emu.gusdma, GUS_read_DMA, s); DMA_register_channel (s->emu.gusdma, GUS_read_DMA, s);
s->emu.himemaddr = s->himem; s->emu.himemaddr = s->himem;

8
hw/sb16.c
View File

@ -1368,20 +1368,20 @@ static int sb16_initfn (ISADevice *dev)
for (i = 0; i < ARRAY_SIZE (dsp_write_ports); i++) { for (i = 0; i < ARRAY_SIZE (dsp_write_ports); i++) {
register_ioport_write (s->port + dsp_write_ports[i], 1, 1, dsp_write, s); register_ioport_write (s->port + dsp_write_ports[i], 1, 1, dsp_write, s);
isa_init_ioport(dev, s->port + dsp_write_ports[i]); isa_init_ioport (dev, s->port + dsp_write_ports[i]);
} }
for (i = 0; i < ARRAY_SIZE (dsp_read_ports); i++) { for (i = 0; i < ARRAY_SIZE (dsp_read_ports); i++) {
register_ioport_read (s->port + dsp_read_ports[i], 1, 1, dsp_read, s); register_ioport_read (s->port + dsp_read_ports[i], 1, 1, dsp_read, s);
isa_init_ioport(dev, s->port + dsp_read_ports[i]); isa_init_ioport (dev, s->port + dsp_read_ports[i]);
} }
register_ioport_write (s->port + 0x4, 1, 1, mixer_write_indexb, s); register_ioport_write (s->port + 0x4, 1, 1, mixer_write_indexb, s);
register_ioport_write (s->port + 0x4, 1, 2, mixer_write_indexw, s); register_ioport_write (s->port + 0x4, 1, 2, mixer_write_indexw, s);
isa_init_ioport(dev, s->port + 0x4); isa_init_ioport (dev, s->port + 0x4);
register_ioport_read (s->port + 0x5, 1, 1, mixer_read, s); register_ioport_read (s->port + 0x5, 1, 1, mixer_read, s);
register_ioport_write (s->port + 0x5, 1, 1, mixer_write_datab, s); register_ioport_write (s->port + 0x5, 1, 1, mixer_write_datab, s);
isa_init_ioport(dev, s->port + 0x5); isa_init_ioport (dev, s->port + 0x5);
DMA_register_channel (s->hdma, SB_read_DMA, s); DMA_register_channel (s->hdma, SB_read_DMA, s);
DMA_register_channel (s->dma, SB_read_DMA, s); DMA_register_channel (s->dma, SB_read_DMA, s);