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Hexagon (tests/tcg/hexagon) fix inline asm in preg_alias.c 

Replace consecutive inline asm blocks with a single one with proper
outputs/inputs/clobbers rather than making assumptions about register
values being carried between separate blocks.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20220210021556.9217-10-tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson 2022-02-09 18:15:53 -08:00
parent 8576e7ecae
commit 8af2d9978a
1 changed files with 21 additions and 23 deletions
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44
tests/tcg/hexagon/preg_alias.c
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@ -1,5 +1,5 @@
/* /*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -57,17 +57,15 @@ typedef union {
static inline void creg_alias(int cval, PRegs *pregs) static inline void creg_alias(int cval, PRegs *pregs)
{ {
unsigned char val; asm("c4 = %4\n\t"
asm volatile("c4 = %0" : : "r"(cval)); "%0 = p0\n\t"
"%1 = p1\n\t"
asm volatile("%0 = p0" : "=r"(val)); "%2 = p2\n\t"
pregs->pregs.p0 = val; "%3 = p3\n\t"
asm volatile("%0 = p1" : "=r"(val)); : "=r"(pregs->pregs.p0), "=r"(pregs->pregs.p1),
pregs->pregs.p1 = val; "=r"(pregs->pregs.p2), "=r"(pregs->pregs.p3)
asm volatile("%0 = p2" : "=r"(val)); : "r"(cval)
pregs->pregs.p2 = val; : "p0", "p1", "p2", "p3");
asm volatile("%0 = p3" : "=r"(val));
pregs->pregs.p3 = val;
} }
int err; int err;
@ -83,19 +81,19 @@ static void check(int val, int expect)
static inline void creg_alias_pair(unsigned int cval, PRegs *pregs) static inline void creg_alias_pair(unsigned int cval, PRegs *pregs)
{ {
unsigned long long cval_pair = (0xdeadbeefULL << 32) | cval; unsigned long long cval_pair = (0xdeadbeefULL << 32) | cval;
unsigned char val;
int c5; int c5;
asm volatile("c5:4 = %0" : : "r"(cval_pair));
asm volatile("%0 = p0" : "=r"(val)); asm ("c5:4 = %5\n\t"
pregs->pregs.p0 = val; "%0 = p0\n\t"
asm volatile("%0 = p1" : "=r"(val)); "%1 = p1\n\t"
pregs->pregs.p1 = val; "%2 = p2\n\t"
asm volatile("%0 = p2" : "=r"(val)); "%3 = p3\n\t"
pregs->pregs.p2 = val; "%4 = c5\n\t"
asm volatile("%0 = p3" : "=r"(val)); : "=r"(pregs->pregs.p0), "=r"(pregs->pregs.p1),
pregs->pregs.p3 = val; "=r"(pregs->pregs.p2), "=r"(pregs->pregs.p3), "=r"(c5)
asm volatile("%0 = c5" : "=r"(c5)); : "r"(cval_pair)
: "p0", "p1", "p2", "p3");
check(c5, 0xdeadbeef); check(c5, 0xdeadbeef);
} }