target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-19-f4bug@amsat.org>
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@ -165,7 +165,6 @@ void r4k_helper_tlbr(CPUMIPSState *env);
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void r4k_helper_tlbinv(CPUMIPSState *env);
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void r4k_helper_tlbinvf(CPUMIPSState *env);
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void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
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uint32_t cpu_mips_get_random(CPUMIPSState *env);
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void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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@ -237,9 +236,6 @@ void cpu_mips_stop_count(CPUMIPSState *env);
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/* helper.c */
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void mmu_init(CPUMIPSState *env, const mips_def_t *def);
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/* op_helper.c */
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void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
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static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
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{
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env->active_tc.PC = value & ~(target_ulong)1;
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@ -11,10 +11,19 @@
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#define MIPS_TCG_INTERNAL_H
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#include "hw/core/cpu.h"
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#include "cpu.h"
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void mips_cpu_do_interrupt(CPUState *cpu);
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bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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#if !defined(CONFIG_USER_ONLY)
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void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
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uint32_t cpu_mips_get_random(CPUMIPSState *env);
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#endif /* !CONFIG_USER_ONLY */
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#endif
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