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target/ppc: Add new PMC HFLAGS

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Add 2 new PMC related HFLAGS:
- HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit
- HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled

These flags allow further optimization of PMC5 update code, by
allowing frequently tested conditions to be performed at
translation time.

Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221025202424.195984-3-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Leandro Lupori 2022-10-25 17:24:23 -03:00 committed by Daniel Henrique Barboza
parent 286787f105
commit 8b3d1c49a9
3 changed files with 13 additions and 1 deletions
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4
target/ppc/cpu.h
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@ -696,7 +696,9 @@ enum {
HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_PR = 14, /* MSR_PR */
HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */ HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */ HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */

6
target/ppc/helper_regs.c
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@ -109,6 +109,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) {
hflags |= 1 << HFLAGS_PMCC1; hflags |= 1 << HFLAGS_PMCC1;
} }
if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) {
hflags |= 1 << HFLAGS_PMCJCE;
}
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
@ -119,6 +122,9 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env)
if (env->pmc_ins_cnt) { if (env->pmc_ins_cnt) {
hflags |= 1 << HFLAGS_INSN_CNT; hflags |= 1 << HFLAGS_INSN_CNT;
} }
if (env->pmc_ins_cnt & 0x1e) {
hflags |= 1 << HFLAGS_PMC_OTHER;
}
#endif #endif
/* /*

4
target/ppc/translate.c
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@ -177,6 +177,8 @@ struct DisasContext {
bool hr; bool hr;
bool mmcr0_pmcc0; bool mmcr0_pmcc0;
bool mmcr0_pmcc1; bool mmcr0_pmcc1;
bool mmcr0_pmcjce;
bool pmc_other;
bool pmu_insn_cnt; bool pmu_insn_cnt;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled; int singlestep_enabled;
@ -7512,6 +7514,8 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->hr = (hflags >> HFLAGS_HR) & 1; ctx->hr = (hflags >> HFLAGS_HR) & 1;
ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1;
ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1;
ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
ctx->singlestep_enabled = 0; ctx->singlestep_enabled = 0;