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target/xtensa: tests: clean up interrupt tests

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Don't use hardcoded software interrupt masks, use XCHAL macros.
Mask off timer interrupt bits that are not checked for.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2016-09-05 22:49:38 -07:00
parent 255d254382
commit 8b912ff033
1 changed files with 20 additions and 7 deletions
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27
tests/tcg/xtensa/test_interrupt.S
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@ -1,5 +1,7 @@
#include "macros.inc" #include "macros.inc"
#define LSBIT(v) ((v) ^ ((v) & ((v) - 1)))
test_suite interrupt test_suite interrupt
.macro clear_interrupts .macro clear_interrupts
@ -46,14 +48,17 @@ test soft_disabled
set_vector kernel, 1f set_vector kernel, 1f
clear_interrupts clear_interrupts
movi a2, 0x80 movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
wsr a2, intset wsr a2, intset
esync esync
rsr a3, interrupt rsr a3, interrupt
movi a4, ~XCHAL_INTTYPE_MASK_TIMER
and a3, a3, a4
assert eq, a2, a3 assert eq, a2, a3
wsr a2, intclear wsr a2, intclear
esync esync
rsr a3, interrupt rsr a3, interrupt
and a3, a3, a4
assert eqi, a3, 0 assert eqi, a3, 0
j 2f j 2f
1: 1:
@ -65,10 +70,12 @@ test soft_intenable
set_vector kernel, 1f set_vector kernel, 1f
clear_interrupts clear_interrupts
movi a2, 0x80 movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
wsr a2, intset wsr a2, intset
esync esync
rsr a3, interrupt rsr a3, interrupt
movi a4, ~XCHAL_INTTYPE_MASK_TIMER
and a3, a3, a4
assert eq, a2, a3 assert eq, a2, a3
rsil a3, 0 rsil a3, 0
wsr a2, intenable wsr a2, intenable
@ -82,10 +89,12 @@ test soft_rsil
set_vector kernel, 1f set_vector kernel, 1f
clear_interrupts clear_interrupts
movi a2, 0x80 movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
wsr a2, intset wsr a2, intset
esync esync
rsr a3, interrupt rsr a3, interrupt
movi a4, ~XCHAL_INTTYPE_MASK_TIMER
and a3, a3, a4
assert eq, a2, a3 assert eq, a2, a3
wsr a2, intenable wsr a2, intenable
rsil a3, 0 rsil a3, 0
@ -99,10 +108,12 @@ test soft_waiti
set_vector kernel, 1f set_vector kernel, 1f
clear_interrupts clear_interrupts
movi a2, 0x80 movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
wsr a2, intset wsr a2, intset
esync esync
rsr a3, interrupt rsr a3, interrupt
movi a4, ~XCHAL_INTTYPE_MASK_TIMER
and a3, a3, a4
assert eq, a2, a3 assert eq, a2, a3
wsr a2, intenable wsr a2, intenable
waiti 0 waiti 0
@ -116,10 +127,12 @@ test soft_user
set_vector user, 2f set_vector user, 2f
clear_interrupts clear_interrupts
movi a2, 0x80 movi a2, LSBIT(XCHAL_INTTYPE_MASK_SOFTWARE)
wsr a2, intset wsr a2, intset
esync esync
rsr a3, interrupt rsr a3, interrupt
movi a4, ~XCHAL_INTTYPE_MASK_TIMER
and a3, a3, a4
assert eq, a2, a3 assert eq, a2, a3
wsr a2, intenable wsr a2, intenable
@ -139,7 +152,7 @@ test soft_priority
set_vector level3, 2f set_vector level3, 2f
clear_interrupts clear_interrupts
movi a2, 0x880 movi a2, XCHAL_INTTYPE_MASK_SOFTWARE
wsr a2, intenable wsr a2, intenable
rsil a3, 0 rsil a3, 0
esync esync
@ -161,7 +174,7 @@ test eps_epc_rfi
clear_interrupts clear_interrupts
reset_ps reset_ps
movi a2, 0x880 movi a2, XCHAL_INTTYPE_MASK_SOFTWARE
wsr a2, intenable wsr a2, intenable
rsil a3, 0 rsil a3, 0
rsr a3, ps rsr a3, ps