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tests/tcg/tricore: Extended and non-extened regs now match 

RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-2-kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-09-13 12:53:17 +02:00
parent 4f79db4750
commit 8c3cf3f2bd
1 changed files with 19 additions and 19 deletions
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38
tests/tcg/tricore/asm/macros.h
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@ -12,31 +12,31 @@
#define TESTDEV_ADDR 0xf0000000 #define TESTDEV_ADDR 0xf0000000
/* Register definitions */ /* Register definitions */
#define DREG_RS1 %d0 #define DREG_RS1 %d0
#define DREG_RS2 %d1 #define DREG_RS2 %d2
#define DREG_RS3 %d2 #define DREG_RS3 %d4
#define DREG_CALC_RESULT %d3 #define DREG_CALC_RESULT %d5
#define DREG_CALC_PSW %d4 #define DREG_CALC_PSW %d6
#define DREG_CORRECT_PSW %d5 #define DREG_CORRECT_PSW %d7
#define DREG_TEMP_LI %d10 #define DREG_TEMP_LI %d13
#define DREG_TEMP %d11 #define DREG_TEMP %d14
#define DREG_TEST_NUM %d14 #define DREG_TEST_NUM %d8
#define DREG_CORRECT_RESULT %d15 #define DREG_CORRECT_RESULT %d9
#define DREG_CORRECT_RESULT_2 %d13 #define DREG_CORRECT_RESULT_2 %d10
#define AREG_ADDR %a0 #define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3 #define AREG_CORRECT_RESULT %a3
#define DREG_DEV_ADDR %a15 #define DREG_DEV_ADDR %a15
#define EREG_RS1 %e6 #define EREG_RS1 %e0
#define EREG_RS1_LO %d6 #define EREG_RS1_LO %d0
#define EREG_RS1_HI %d7 #define EREG_RS1_HI %d1
#define EREG_RS2 %e8 #define EREG_RS2 %e2
#define EREG_RS2_LO %d8 #define EREG_RS2_LO %d2
#define EREG_RS2_HI %d9 #define EREG_RS2_HI %d3
#define EREG_CALC_RESULT %e8 #define EREG_CALC_RESULT %e6
#define EREG_CALC_RESULT_HI %d9 #define EREG_CALC_RESULT_LO %d6
#define EREG_CALC_RESULT_LO %d8 #define EREG_CALC_RESULT_HI %d7
#define EREG_CORRECT_RESULT_LO %d0 #define EREG_CORRECT_RESULT_LO %d0
#define EREG_CORRECT_RESULT_HI %d1 #define EREG_CORRECT_RESULT_HI %d1