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Initial commit of tcg/loongarch64 

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Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7680/qemu into staging

Initial commit of tcg/loongarch64

# gpg: Signature made Tue 21 Dec 2021 01:19:00 PM PST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-loong-20211221-2' of https://gitlab.com/rth7680/qemu: (30 commits)
  configure, meson.build: Mark support for loongarch64 hosts
  linux-user: Implement CPU-specific signal handler for loongarch64 hosts
  common-user: Add safe syscall handling for loongarch64 hosts
  tcg/loongarch64: Register the JIT
  tcg/loongarch64: Implement tcg_target_init
  tcg/loongarch64: Implement exit_tb/goto_tb
  tcg/loongarch64: Implement tcg_target_qemu_prologue
  tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops
  tcg/loongarch64: Implement simple load/store ops
  tcg/loongarch64: Implement tcg_out_call
  tcg/loongarch64: Implement setcond ops
  tcg/loongarch64: Implement br/brcond ops
  tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops
  tcg/loongarch64: Implement add/sub ops
  tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops
  tcg/loongarch64: Implement clz/ctz ops
  tcg/loongarch64: Implement bswap{16,32,64} ops
  tcg/loongarch64: Implement deposit/extract ops
  tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops
  tcg/loongarch64: Implement sign-/zero-extension ops
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-12-21 13:30:35 -08:00
parent 5316e12bb2 dfcf900ba6
commit 8c5f94cd41
11 changed files with 3085 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -3143,6 +3143,11 @@ S: Maintained
F: tcg/i386/
F: disas/i386.c
LoongArch64 TCG target
M: WANG Xuerui <git@xen0n.name>
S: Maintained
F: tcg/loongarch64/
MIPS TCG target
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
R: Aurelien Jarno <aurelien@aurel32.net>

90
common-user/host/loongarch64/safe-syscall.inc.S Normal file
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@ -0,0 +1,90 @@
/*
* safe-syscall.inc.S : host-specific assembly fragment
* to handle signals occurring at the same time as system calls.
* This is intended to be included by common-user/safe-syscall.S
*
* Ported to LoongArch by WANG Xuerui <git@xen0n.name>
*
* Based on safe-syscall.inc.S code for RISC-V,
* originally written by Richard Henderson <rth@twiddle.net>
* Copyright (C) 2018 Linaro, Inc.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
.global safe_syscall_base
.global safe_syscall_start
.global safe_syscall_end
.type safe_syscall_base, @function
.type safe_syscall_start, @function
.type safe_syscall_end, @function
/*
* This is the entry point for making a system call. The calling
* convention here is that of a C varargs function with the
* first argument an 'int *' to the signal_pending flag, the
* second one the system call number (as a 'long'), and all further
* arguments being syscall arguments (also 'long').
*/
safe_syscall_base:
.cfi_startproc
/*
* The syscall calling convention is nearly the same as C:
* we enter with a0 == &signal_pending
* a1 == syscall number
* a2 ... a7 == syscall arguments
* and return the result in a0
* and the syscall instruction needs
* a7 == syscall number
* a0 ... a5 == syscall arguments
* and returns the result in a0
* Shuffle everything around appropriately.
*/
move $t0, $a0 /* signal_pending pointer */
move $t1, $a1 /* syscall number */
move $a0, $a2 /* syscall arguments */
move $a1, $a3
move $a2, $a4
move $a3, $a5
move $a4, $a6
move $a5, $a7
move $a7, $t1
/*
* We need to preserve the signal_pending pointer but t0 is
* clobbered by syscalls on LoongArch, so we need to move it
* somewhere else, ideally both preserved across syscalls and
* clobbered by procedure calls so we don't have to allocate a
* stack frame; a6 is just the register we want here.
*/
move $a6, $t0
/*
* This next sequence of code works in conjunction with the
* rewind_if_safe_syscall_function(). If a signal is taken
* and the interrupted PC is anywhere between 'safe_syscall_start'
* and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'.
* The code sequence must therefore be able to cope with this, and
* the syscall instruction must be the final one in the sequence.
*/
safe_syscall_start:
/* If signal_pending is non-zero, don't do the call */
ld.w $t1, $a6, 0
bnez $t1, 2f
syscall 0
safe_syscall_end:
/* code path for having successfully executed the syscall */
li.w $t2, -4096
bgtu $a0, $t2, 0f
jr $ra
/* code path setting errno */
0: sub.d $a0, $zero, $a0
b safe_syscall_set_errno_tail
/* code path when we didn't execute the syscall */
2: li.w $a0, QEMU_ERESTARTSYS
b safe_syscall_set_errno_tail
.cfi_endproc
.size safe_syscall_base, .-safe_syscall_base

5
configure vendored
View File

@ -631,6 +631,8 @@ elif check_define __arm__ ; then
cpu="arm"
elif check_define __aarch64__ ; then
cpu="aarch64"
elif check_define __loongarch64 ; then
cpu="loongarch64"
else
cpu=$(uname -m)
fi
@ -3720,6 +3722,9 @@ if test "$linux" = "yes" ; then
aarch64)
linux_arch=arm64
;;
loongarch*)
linux_arch=loongarch
;;
mips64)
linux_arch=mips
;;

2
include/elf.h
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@ -182,6 +182,8 @@ typedef struct mips_elf_abiflags_v0 {
#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */
#define EM_LOONGARCH 258 /* LoongArch */
/*
* This is an interim value that we will use until the committee comes
* up with a final number.

87
linux-user/host/loongarch64/host-signal.h Normal file
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@ -0,0 +1,87 @@
/*
* host-signal.h: signal info dependent on the host architecture
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef LOONGARCH64_HOST_SIGNAL_H
#define LOONGARCH64_HOST_SIGNAL_H
static inline uintptr_t host_signal_pc(ucontext_t *uc)
{
return uc->uc_mcontext.__pc;
}
static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc)
{
uc->uc_mcontext.__pc = pc;
}
static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
{
const uint32_t *pinsn = (const uint32_t *)host_signal_pc(uc);
uint32_t insn = pinsn[0];
/* Detect store by reading the instruction at the program counter. */
switch ((insn >> 26) & 0b111111) {
case 0b001000: /* {ll,sc}.[wd] */
switch ((insn >> 24) & 0b11) {
case 0b01: /* sc.w */
case 0b11: /* sc.d */
return true;
}
break;
case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */
switch ((insn >> 24) & 0b11) {
case 0b01: /* stox4.w (stptr.w) */
case 0b11: /* stox4.d (stptr.d) */
return true;
}
break;
case 0b001010: /* {ld,st}.* family */
switch ((insn >> 22) & 0b1111) {
case 0b0100: /* st.b */
case 0b0101: /* st.h */
case 0b0110: /* st.w */
case 0b0111: /* st.d */
case 0b1101: /* fst.s */
case 0b1111: /* fst.d */
return true;
}
break;
case 0b001110: /* indexed, atomic, bounds-checking memory operations */
uint32_t sel = (insn >> 15) & 0b11111111111;
switch (sel) {
case 0b00000100000: /* stx.b */
case 0b00000101000: /* stx.h */
case 0b00000110000: /* stx.w */
case 0b00000111000: /* stx.d */
case 0b00001110000: /* fstx.s */
case 0b00001111000: /* fstx.d */
case 0b00011101100: /* fstgt.s */
case 0b00011101101: /* fstgt.d */
case 0b00011101110: /* fstle.s */
case 0b00011101111: /* fstle.d */
case 0b00011111000: /* stgt.b */
case 0b00011111001: /* stgt.h */
case 0b00011111010: /* stgt.w */
case 0b00011111011: /* stgt.d */
case 0b00011111100: /* stle.b */
case 0b00011111101: /* stle.h */
case 0b00011111110: /* stle.w */
case 0b00011111111: /* stle.d */
case 0b00011000000 ... 0b00011100011: /* am* insns */
return true;
}
break;
}
return false;
}
#endif

2
meson.build
View File

@ -56,7 +56,7 @@ python = import('python').find_installation()
supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux']
supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
'arm', 'aarch64', 'loongarch64', 'mips', 'mips64', 'sparc', 'sparc64']
cpu = host_machine.cpu_family()

979
tcg/loongarch64/tcg-insn-defs.c.inc Normal file
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@ -0,0 +1,979 @@
/* SPDX-License-Identifier: MIT */
/*
* LoongArch instruction formats, opcodes, and encoders for TCG use.
*
* This file is auto-generated by genqemutcgdefs from
* https://github.com/loongson-community/loongarch-opcodes,
* from commit 961f0c60f5b63e574d785995600c71ad5413fdc4.
* DO NOT EDIT.
*/
typedef enum {
OPC_CLZ_W = 0x00001400,
OPC_CTZ_W = 0x00001c00,
OPC_CLZ_D = 0x00002400,
OPC_CTZ_D = 0x00002c00,
OPC_REVB_2H = 0x00003000,
OPC_REVB_2W = 0x00003800,
OPC_REVB_D = 0x00003c00,
OPC_SEXT_H = 0x00005800,
OPC_SEXT_B = 0x00005c00,
OPC_ADD_W = 0x00100000,
OPC_ADD_D = 0x00108000,
OPC_SUB_W = 0x00110000,
OPC_SUB_D = 0x00118000,
OPC_SLT = 0x00120000,
OPC_SLTU = 0x00128000,
OPC_MASKEQZ = 0x00130000,
OPC_MASKNEZ = 0x00138000,
OPC_NOR = 0x00140000,
OPC_AND = 0x00148000,
OPC_OR = 0x00150000,
OPC_XOR = 0x00158000,
OPC_ORN = 0x00160000,
OPC_ANDN = 0x00168000,
OPC_SLL_W = 0x00170000,
OPC_SRL_W = 0x00178000,
OPC_SRA_W = 0x00180000,
OPC_SLL_D = 0x00188000,
OPC_SRL_D = 0x00190000,
OPC_SRA_D = 0x00198000,
OPC_ROTR_W = 0x001b0000,
OPC_ROTR_D = 0x001b8000,
OPC_MUL_W = 0x001c0000,
OPC_MULH_W = 0x001c8000,
OPC_MULH_WU = 0x001d0000,
OPC_MUL_D = 0x001d8000,
OPC_MULH_D = 0x001e0000,
OPC_MULH_DU = 0x001e8000,
OPC_DIV_W = 0x00200000,
OPC_MOD_W = 0x00208000,
OPC_DIV_WU = 0x00210000,
OPC_MOD_WU = 0x00218000,
OPC_DIV_D = 0x00220000,
OPC_MOD_D = 0x00228000,
OPC_DIV_DU = 0x00230000,
OPC_MOD_DU = 0x00238000,
OPC_SLLI_W = 0x00408000,
OPC_SLLI_D = 0x00410000,
OPC_SRLI_W = 0x00448000,
OPC_SRLI_D = 0x00450000,
OPC_SRAI_W = 0x00488000,
OPC_SRAI_D = 0x00490000,
OPC_ROTRI_W = 0x004c8000,
OPC_ROTRI_D = 0x004d0000,
OPC_BSTRINS_W = 0x00600000,
OPC_BSTRPICK_W = 0x00608000,
OPC_BSTRINS_D = 0x00800000,
OPC_BSTRPICK_D = 0x00c00000,
OPC_SLTI = 0x02000000,
OPC_SLTUI = 0x02400000,
OPC_ADDI_W = 0x02800000,
OPC_ADDI_D = 0x02c00000,
OPC_CU52I_D = 0x03000000,
OPC_ANDI = 0x03400000,
OPC_ORI = 0x03800000,
OPC_XORI = 0x03c00000,
OPC_LU12I_W = 0x14000000,
OPC_CU32I_D = 0x16000000,
OPC_PCADDU2I = 0x18000000,
OPC_PCALAU12I = 0x1a000000,
OPC_PCADDU12I = 0x1c000000,
OPC_PCADDU18I = 0x1e000000,
OPC_LD_B = 0x28000000,
OPC_LD_H = 0x28400000,
OPC_LD_W = 0x28800000,
OPC_LD_D = 0x28c00000,
OPC_ST_B = 0x29000000,
OPC_ST_H = 0x29400000,
OPC_ST_W = 0x29800000,
OPC_ST_D = 0x29c00000,
OPC_LD_BU = 0x2a000000,
OPC_LD_HU = 0x2a400000,
OPC_LD_WU = 0x2a800000,
OPC_LDX_B = 0x38000000,
OPC_LDX_H = 0x38040000,
OPC_LDX_W = 0x38080000,
OPC_LDX_D = 0x380c0000,
OPC_STX_B = 0x38100000,
OPC_STX_H = 0x38140000,
OPC_STX_W = 0x38180000,
OPC_STX_D = 0x381c0000,
OPC_LDX_BU = 0x38200000,
OPC_LDX_HU = 0x38240000,
OPC_LDX_WU = 0x38280000,
OPC_DBAR = 0x38720000,
OPC_JIRL = 0x4c000000,
OPC_B = 0x50000000,
OPC_BL = 0x54000000,
OPC_BEQ = 0x58000000,
OPC_BNE = 0x5c000000,
OPC_BGT = 0x60000000,
OPC_BLE = 0x64000000,
OPC_BGTU = 0x68000000,
OPC_BLEU = 0x6c000000,
} LoongArchInsn;
static int32_t __attribute__((unused))
encode_d_slot(LoongArchInsn opc, uint32_t d)
{
return opc | d;
}
static int32_t __attribute__((unused))
encode_dj_slots(LoongArchInsn opc, uint32_t d, uint32_t j)
{
return opc | d | j << 5;
}
static int32_t __attribute__((unused))
encode_djk_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k)
{
return opc | d | j << 5 | k << 10;
}
static int32_t __attribute__((unused))
encode_djkm_slots(LoongArchInsn opc, uint32_t d, uint32_t j, uint32_t k,
uint32_t m)
{
return opc | d | j << 5 | k << 10 | m << 16;
}
static int32_t __attribute__((unused))
encode_dk_slots(LoongArchInsn opc, uint32_t d, uint32_t k)
{
return opc | d | k << 10;
}
static int32_t __attribute__((unused))
encode_dj_insn(LoongArchInsn opc, TCGReg d, TCGReg j)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
return encode_dj_slots(opc, d, j);
}
static int32_t __attribute__((unused))
encode_djk_insn(LoongArchInsn opc, TCGReg d, TCGReg j, TCGReg k)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(k >= 0 && k <= 0x1f);
return encode_djk_slots(opc, d, j, k);
}
static int32_t __attribute__((unused))
encode_djsk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(sk12 >= -0x800 && sk12 <= 0x7ff);
return encode_djk_slots(opc, d, j, sk12 & 0xfff);
}
static int32_t __attribute__((unused))
encode_djsk16_insn(LoongArchInsn opc, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(sk16 >= -0x8000 && sk16 <= 0x7fff);
return encode_djk_slots(opc, d, j, sk16 & 0xffff);
}
static int32_t __attribute__((unused))
encode_djuk12_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk12)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(uk12 <= 0xfff);
return encode_djk_slots(opc, d, j, uk12);
}
static int32_t __attribute__((unused))
encode_djuk5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(uk5 <= 0x1f);
return encode_djk_slots(opc, d, j, uk5);
}
static int32_t __attribute__((unused))
encode_djuk5um5_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk5,
uint32_t um5)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(uk5 <= 0x1f);
tcg_debug_assert(um5 <= 0x1f);
return encode_djkm_slots(opc, d, j, uk5, um5);
}
static int32_t __attribute__((unused))
encode_djuk6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(uk6 <= 0x3f);
return encode_djk_slots(opc, d, j, uk6);
}
static int32_t __attribute__((unused))
encode_djuk6um6_insn(LoongArchInsn opc, TCGReg d, TCGReg j, uint32_t uk6,
uint32_t um6)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(j >= 0 && j <= 0x1f);
tcg_debug_assert(uk6 <= 0x3f);
tcg_debug_assert(um6 <= 0x3f);
return encode_djkm_slots(opc, d, j, uk6, um6);
}
static int32_t __attribute__((unused))
encode_dsj20_insn(LoongArchInsn opc, TCGReg d, int32_t sj20)
{
tcg_debug_assert(d >= 0 && d <= 0x1f);
tcg_debug_assert(sj20 >= -0x80000 && sj20 <= 0x7ffff);
return encode_dj_slots(opc, d, sj20 & 0xfffff);
}
static int32_t __attribute__((unused))
encode_sd10k16_insn(LoongArchInsn opc, int32_t sd10k16)
{
tcg_debug_assert(sd10k16 >= -0x2000000 && sd10k16 <= 0x1ffffff);
return encode_dk_slots(opc, (sd10k16 >> 16) & 0x3ff, sd10k16 & 0xffff);
}
static int32_t __attribute__((unused))
encode_ud15_insn(LoongArchInsn opc, uint32_t ud15)
{
tcg_debug_assert(ud15 <= 0x7fff);
return encode_d_slot(opc, ud15);
}
/* Emits the `clz.w d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_clz_w(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CLZ_W, d, j));
}
/* Emits the `ctz.w d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_ctz_w(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CTZ_W, d, j));
}
/* Emits the `clz.d d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_clz_d(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CLZ_D, d, j));
}
/* Emits the `ctz.d d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_ctz_d(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_CTZ_D, d, j));
}
/* Emits the `revb.2h d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_revb_2h(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_2H, d, j));
}
/* Emits the `revb.2w d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_revb_2w(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_2W, d, j));
}
/* Emits the `revb.d d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_revb_d(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_REVB_D, d, j));
}
/* Emits the `sext.h d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_sext_h(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_SEXT_H, d, j));
}
/* Emits the `sext.b d, j` instruction. */
static void __attribute__((unused))
tcg_out_opc_sext_b(TCGContext *s, TCGReg d, TCGReg j)
{
tcg_out32(s, encode_dj_insn(OPC_SEXT_B, d, j));
}
/* Emits the `add.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_add_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ADD_W, d, j, k));
}
/* Emits the `add.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_add_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ADD_D, d, j, k));
}
/* Emits the `sub.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sub_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SUB_W, d, j, k));
}
/* Emits the `sub.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sub_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SUB_D, d, j, k));
}
/* Emits the `slt d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_slt(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLT, d, j, k));
}
/* Emits the `sltu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sltu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLTU, d, j, k));
}
/* Emits the `maskeqz d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_maskeqz(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MASKEQZ, d, j, k));
}
/* Emits the `masknez d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_masknez(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MASKNEZ, d, j, k));
}
/* Emits the `nor d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_nor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_NOR, d, j, k));
}
/* Emits the `and d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_and(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_AND, d, j, k));
}
/* Emits the `or d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_or(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_OR, d, j, k));
}
/* Emits the `xor d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_xor(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_XOR, d, j, k));
}
/* Emits the `orn d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_orn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ORN, d, j, k));
}
/* Emits the `andn d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_andn(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ANDN, d, j, k));
}
/* Emits the `sll.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sll_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLL_W, d, j, k));
}
/* Emits the `srl.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_srl_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRL_W, d, j, k));
}
/* Emits the `sra.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sra_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRA_W, d, j, k));
}
/* Emits the `sll.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sll_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SLL_D, d, j, k));
}
/* Emits the `srl.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_srl_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRL_D, d, j, k));
}
/* Emits the `sra.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_sra_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_SRA_D, d, j, k));
}
/* Emits the `rotr.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_rotr_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_W, d, j, k));
}
/* Emits the `rotr.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_rotr_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_ROTR_D, d, j, k));
}
/* Emits the `mul.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mul_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MUL_W, d, j, k));
}
/* Emits the `mulh.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mulh_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_W, d, j, k));
}
/* Emits the `mulh.wu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mulh_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_WU, d, j, k));
}
/* Emits the `mul.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mul_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MUL_D, d, j, k));
}
/* Emits the `mulh.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mulh_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_D, d, j, k));
}
/* Emits the `mulh.du d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mulh_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MULH_DU, d, j, k));
}
/* Emits the `div.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_div_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_W, d, j, k));
}
/* Emits the `mod.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mod_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_W, d, j, k));
}
/* Emits the `div.wu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_div_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_WU, d, j, k));
}
/* Emits the `mod.wu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mod_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_WU, d, j, k));
}
/* Emits the `div.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_div_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_D, d, j, k));
}
/* Emits the `mod.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mod_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_D, d, j, k));
}
/* Emits the `div.du d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_div_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_DIV_DU, d, j, k));
}
/* Emits the `mod.du d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_mod_du(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_MOD_DU, d, j, k));
}
/* Emits the `slli.w d, j, uk5` instruction. */
static void __attribute__((unused))
tcg_out_opc_slli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SLLI_W, d, j, uk5));
}
/* Emits the `slli.d d, j, uk6` instruction. */
static void __attribute__((unused))
tcg_out_opc_slli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SLLI_D, d, j, uk6));
}
/* Emits the `srli.w d, j, uk5` instruction. */
static void __attribute__((unused))
tcg_out_opc_srli_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SRLI_W, d, j, uk5));
}
/* Emits the `srli.d d, j, uk6` instruction. */
static void __attribute__((unused))
tcg_out_opc_srli_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SRLI_D, d, j, uk6));
}
/* Emits the `srai.w d, j, uk5` instruction. */
static void __attribute__((unused))
tcg_out_opc_srai_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_SRAI_W, d, j, uk5));
}
/* Emits the `srai.d d, j, uk6` instruction. */
static void __attribute__((unused))
tcg_out_opc_srai_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_SRAI_D, d, j, uk6));
}
/* Emits the `rotri.w d, j, uk5` instruction. */
static void __attribute__((unused))
tcg_out_opc_rotri_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5)
{
tcg_out32(s, encode_djuk5_insn(OPC_ROTRI_W, d, j, uk5));
}
/* Emits the `rotri.d d, j, uk6` instruction. */
static void __attribute__((unused))
tcg_out_opc_rotri_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6)
{
tcg_out32(s, encode_djuk6_insn(OPC_ROTRI_D, d, j, uk6));
}
/* Emits the `bstrins.w d, j, uk5, um5` instruction. */
static void __attribute__((unused))
tcg_out_opc_bstrins_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5,
uint32_t um5)
{
tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRINS_W, d, j, uk5, um5));
}
/* Emits the `bstrpick.w d, j, uk5, um5` instruction. */
static void __attribute__((unused))
tcg_out_opc_bstrpick_w(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk5,
uint32_t um5)
{
tcg_out32(s, encode_djuk5um5_insn(OPC_BSTRPICK_W, d, j, uk5, um5));
}
/* Emits the `bstrins.d d, j, uk6, um6` instruction. */
static void __attribute__((unused))
tcg_out_opc_bstrins_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6,
uint32_t um6)
{
tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRINS_D, d, j, uk6, um6));
}
/* Emits the `bstrpick.d d, j, uk6, um6` instruction. */
static void __attribute__((unused))
tcg_out_opc_bstrpick_d(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk6,
uint32_t um6)
{
tcg_out32(s, encode_djuk6um6_insn(OPC_BSTRPICK_D, d, j, uk6, um6));
}
/* Emits the `slti d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_slti(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_SLTI, d, j, sk12));
}
/* Emits the `sltui d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_sltui(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_SLTUI, d, j, sk12));
}
/* Emits the `addi.w d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_addi_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ADDI_W, d, j, sk12));
}
/* Emits the `addi.d d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_addi_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ADDI_D, d, j, sk12));
}
/* Emits the `cu52i.d d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_cu52i_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_CU52I_D, d, j, sk12));
}
/* Emits the `andi d, j, uk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_andi(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_ANDI, d, j, uk12));
}
/* Emits the `ori d, j, uk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_ORI, d, j, uk12));
}
/* Emits the `xori d, j, uk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_xori(TCGContext *s, TCGReg d, TCGReg j, uint32_t uk12)
{
tcg_out32(s, encode_djuk12_insn(OPC_XORI, d, j, uk12));
}
/* Emits the `lu12i.w d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_lu12i_w(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_LU12I_W, d, sj20));
}
/* Emits the `cu32i.d d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_cu32i_d(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_CU32I_D, d, sj20));
}
/* Emits the `pcaddu2i d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_pcaddu2i(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_PCADDU2I, d, sj20));
}
/* Emits the `pcalau12i d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_pcalau12i(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_PCALAU12I, d, sj20));
}
/* Emits the `pcaddu12i d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_pcaddu12i(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_PCADDU12I, d, sj20));
}
/* Emits the `pcaddu18i d, sj20` instruction. */
static void __attribute__((unused))
tcg_out_opc_pcaddu18i(TCGContext *s, TCGReg d, int32_t sj20)
{
tcg_out32(s, encode_dsj20_insn(OPC_PCADDU18I, d, sj20));
}
/* Emits the `ld.b d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_B, d, j, sk12));
}
/* Emits the `ld.h d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_H, d, j, sk12));
}
/* Emits the `ld.w d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_W, d, j, sk12));
}
/* Emits the `ld.d d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_D, d, j, sk12));
}
/* Emits the `st.b d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_st_b(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_B, d, j, sk12));
}
/* Emits the `st.h d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_st_h(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_H, d, j, sk12));
}
/* Emits the `st.w d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_st_w(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_W, d, j, sk12));
}
/* Emits the `st.d d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_st_d(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_ST_D, d, j, sk12));
}
/* Emits the `ld.bu d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_bu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_BU, d, j, sk12));
}
/* Emits the `ld.hu d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_hu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_HU, d, j, sk12));
}
/* Emits the `ld.wu d, j, sk12` instruction. */
static void __attribute__((unused))
tcg_out_opc_ld_wu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk12)
{
tcg_out32(s, encode_djsk12_insn(OPC_LD_WU, d, j, sk12));
}
/* Emits the `ldx.b d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_B, d, j, k));
}
/* Emits the `ldx.h d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_H, d, j, k));
}
/* Emits the `ldx.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_W, d, j, k));
}
/* Emits the `ldx.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_D, d, j, k));
}
/* Emits the `stx.b d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_stx_b(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_B, d, j, k));
}
/* Emits the `stx.h d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_stx_h(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_H, d, j, k));
}
/* Emits the `stx.w d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_stx_w(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_W, d, j, k));
}
/* Emits the `stx.d d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_stx_d(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_STX_D, d, j, k));
}
/* Emits the `ldx.bu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_bu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_BU, d, j, k));
}
/* Emits the `ldx.hu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_hu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_HU, d, j, k));
}
/* Emits the `ldx.wu d, j, k` instruction. */
static void __attribute__((unused))
tcg_out_opc_ldx_wu(TCGContext *s, TCGReg d, TCGReg j, TCGReg k)
{
tcg_out32(s, encode_djk_insn(OPC_LDX_WU, d, j, k));
}
/* Emits the `dbar ud15` instruction. */
static void __attribute__((unused))
tcg_out_opc_dbar(TCGContext *s, uint32_t ud15)
{
tcg_out32(s, encode_ud15_insn(OPC_DBAR, ud15));
}
/* Emits the `jirl d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_jirl(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_JIRL, d, j, sk16));
}
/* Emits the `b sd10k16` instruction. */
static void __attribute__((unused))
tcg_out_opc_b(TCGContext *s, int32_t sd10k16)
{
tcg_out32(s, encode_sd10k16_insn(OPC_B, sd10k16));
}
/* Emits the `bl sd10k16` instruction. */
static void __attribute__((unused))
tcg_out_opc_bl(TCGContext *s, int32_t sd10k16)
{
tcg_out32(s, encode_sd10k16_insn(OPC_BL, sd10k16));
}
/* Emits the `beq d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_beq(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BEQ, d, j, sk16));
}
/* Emits the `bne d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_bne(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BNE, d, j, sk16));
}
/* Emits the `bgt d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_bgt(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BGT, d, j, sk16));
}
/* Emits the `ble d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_ble(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BLE, d, j, sk16));
}
/* Emits the `bgtu d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_bgtu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BGTU, d, j, sk16));
}
/* Emits the `bleu d, j, sk16` instruction. */
static void __attribute__((unused))
tcg_out_opc_bleu(TCGContext *s, TCGReg d, TCGReg j, int32_t sk16)
{
tcg_out32(s, encode_djsk16_insn(OPC_BLEU, d, j, sk16));
}
/* End of generated code. */

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/* SPDX-License-Identifier: MIT */
/*
* Define LoongArch target-specific constraint sets.
*
* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
*
* Based on tcg/riscv/tcg-target-con-set.h
*
* Copyright (c) 2021 Linaro
*/
/*
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O0_I2(LZ, L)
C_O1_I1(r, r)
C_O1_I1(r, L)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
C_O1_I2(r, rZ, rZ)

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/* SPDX-License-Identifier: MIT */
/*
* Define LoongArch target-specific operand constraints.
*
* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
*
* Based on tcg/riscv/tcg-target-con-str.h
*
* Copyright (c) 2021 Linaro
*/
/*
* Define constraint letters for register sets:
* REGS(letter, register_mask)
*/
REGS('r', ALL_GENERAL_REGS)
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
/*
* Define constraint letters for constants:
* CONST(letter, TCG_CT_CONST_* bit set)
*/
CONST('I', TCG_CT_CONST_S12)
CONST('N', TCG_CT_CONST_N12)
CONST('U', TCG_CT_CONST_U12)
CONST('Z', TCG_CT_CONST_ZERO)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ)

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/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
*
* Based on tcg/riscv/tcg-target.h
*
* Copyright (c) 2018 SiFive, Inc
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef LOONGARCH_TCG_TARGET_H
#define LOONGARCH_TCG_TARGET_H
/*
* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
* for the initial upstreaming of this architecture, so don't bother and just
* support the LP64* ABI for now.
*/
#if defined(__loongarch64)
# define TCG_TARGET_REG_BITS 64
#else
# error unsupported LoongArch register size
#endif
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 32
#define MAX_CODE_GEN_BUFFER_SIZE SIZE_MAX
typedef enum {
TCG_REG_ZERO,
TCG_REG_RA,
TCG_REG_TP,
TCG_REG_SP,
TCG_REG_A0,
TCG_REG_A1,
TCG_REG_A2,
TCG_REG_A3,
TCG_REG_A4,
TCG_REG_A5,
TCG_REG_A6,
TCG_REG_A7,
TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
TCG_REG_T4,
TCG_REG_T5,
TCG_REG_T6,
TCG_REG_T7,
TCG_REG_T8,
TCG_REG_RESERVED,
TCG_REG_S9,
TCG_REG_S0,
TCG_REG_S1,
TCG_REG_S2,
TCG_REG_S3,
TCG_REG_S4,
TCG_REG_S5,
TCG_REG_S6,
TCG_REG_S7,
TCG_REG_S8,
/* aliases */
TCG_AREG0 = TCG_REG_S0,
TCG_REG_TMP0 = TCG_REG_T8,
TCG_REG_TMP1 = TCG_REG_T7,
TCG_REG_TMP2 = TCG_REG_T6,
} TCGReg;
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP
#define TCG_TARGET_STACK_ALIGN 16
#define TCG_TARGET_CALL_ALIGN_ARGS 1
#define TCG_TARGET_CALL_STACK_OFFSET 0
/* optional instructions */
#define TCG_TARGET_HAS_movcond_i32 0
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 1
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 0
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_direct_jump 0
#define TCG_TARGET_HAS_brcond2 0
#define TCG_TARGET_HAS_setcond2 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
/* 64-bit operations */
#define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_extract_i64 1
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_extrl_i64_i32 1
#define TCG_TARGET_HAS_extrh_i64_i32 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 0
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1
#define TCG_TARGET_HAS_ctpop_i64 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
/* not defined -- call should be eliminated at compile time */
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_DEFAULT_MO (0)
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
#endif /* LOONGARCH_TCG_TARGET_H */