target/arm: Implement FEAT_S2FWB
Implement the handling of FEAT_S2FWB; the meat of this is in the new combined_attrs_fwb() function which combines S1 and S2 attributes when HCR_EL2.FWB is set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
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@ -3941,6 +3941,11 @@ static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
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}
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}
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static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
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}
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
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{
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{
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
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@ -5161,6 +5161,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
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if (cpu_isar_feature(aa64_scxtnum, cpu)) {
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if (cpu_isar_feature(aa64_scxtnum, cpu)) {
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valid_mask |= HCR_ENSCXT;
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valid_mask |= HCR_ENSCXT;
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}
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}
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if (cpu_isar_feature(aa64_fwb, cpu)) {
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valid_mask |= HCR_FWB;
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}
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}
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}
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/* Clear RES0 bits. */
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/* Clear RES0 bits. */
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@ -5172,8 +5175,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
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* HCR_PTW forbids certain page-table setups
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* HCR_PTW forbids certain page-table setups
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* HCR_DC disables stage1 and enables stage2 translation
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* HCR_DC disables stage1 and enables stage2 translation
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* HCR_DCT enables tagging on (disabled) stage1 translation
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* HCR_DCT enables tagging on (disabled) stage1 translation
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* HCR_FWB changes the interpretation of stage2 descriptor bits
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*/
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*/
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if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
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if ((env->cp15.hcr_el2 ^ value) &
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(HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) {
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tlb_flush(CPU(cpu));
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tlb_flush(CPU(cpu));
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}
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}
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env->cp15.hcr_el2 = value;
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env->cp15.hcr_el2 = value;
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@ -10731,9 +10736,15 @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
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* attributes are therefore only Device if stage 2 specifies Device.
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* attributes are therefore only Device if stage 2 specifies Device.
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* With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
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* With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
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* ie when cacheattrs.attrs bits [3:2] are 0b00.
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* ie when cacheattrs.attrs bits [3:2] are 0b00.
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* With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
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* when cacheattrs.attrs bit [2] is 0.
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*/
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*/
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assert(cacheattrs.is_s2_format);
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assert(cacheattrs.is_s2_format);
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return (cacheattrs.attrs & 0xc) == 0;
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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return (cacheattrs.attrs & 0x4) == 0;
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} else {
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return (cacheattrs.attrs & 0xc) == 0;
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}
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}
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}
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/* Translate a S1 pagetable walk through S2 if needed. */
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/* Translate a S1 pagetable walk through S2 if needed. */
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@ -12618,6 +12629,69 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env,
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return ret_attrs;
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return ret_attrs;
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}
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}
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static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
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{
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/*
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* Given the 4 bits specifying the outer or inner cacheability
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* in MAIR format, return a value specifying Normal Write-Back,
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* with the allocation and transient hints taken from the input
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* if the input specified some kind of cacheable attribute.
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*/
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if (attr == 0 || attr == 4) {
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/*
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* 0 == an UNPREDICTABLE encoding
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* 4 == Non-cacheable
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* Either way, force Write-Back RW allocate non-transient
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*/
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return 0xf;
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}
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/* Change WriteThrough to WriteBack, keep allocation and transient hints */
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return attr | 4;
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}
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/*
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* Combine the memory type and cacheability attributes of
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* s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
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* combined attributes in MAIR_EL1 format.
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*/
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static uint8_t combined_attrs_fwb(CPUARMState *env,
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ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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switch (s2.attrs) {
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case 7:
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/* Use stage 1 attributes */
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return s1.attrs;
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case 6:
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/*
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* Force Normal Write-Back. Note that if S1 is Normal cacheable
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* then we take the allocation hints from it; otherwise it is
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* RW allocate, non-transient.
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*/
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if ((s1.attrs & 0xf0) == 0) {
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/* S1 is Device */
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return 0xff;
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}
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/* Need to check the Inner and Outer nibbles separately */
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return force_cacheattr_nibble_wb(s1.attrs & 0xf) |
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force_cacheattr_nibble_wb(s1.attrs >> 4) << 4;
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case 5:
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/* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
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if ((s1.attrs & 0xf0) == 0) {
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return s1.attrs;
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}
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return 0x44;
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case 0 ... 3:
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/* Force Device, of subtype specified by S2 */
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return s2.attrs << 2;
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default:
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/*
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* RESERVED values (including RES0 descriptor bit [5] being nonzero);
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* arbitrarily force Device.
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*/
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return 0;
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}
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}
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/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
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/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
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* and CombineS1S2Desc()
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* and CombineS1S2Desc()
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*
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*
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@ -12652,7 +12726,11 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
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}
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}
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/* Combine memory type and cacheability attributes */
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/* Combine memory type and cacheability attributes */
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ret.attrs = combined_attrs_nofwb(env, s1, s2);
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if (arm_hcr_el2_eff(env) & HCR_FWB) {
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ret.attrs = combined_attrs_fwb(env, s1, s2);
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} else {
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ret.attrs = combined_attrs_nofwb(env, s1, s2);
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}
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/*
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/*
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* Any location for which the resultant memory type is any
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* Any location for which the resultant memory type is any
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