target/riscv: Fix vslide1up.vf and vslide1down.vf
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its scalar input should be uint64_t to hold the 64 bits float register.And the same for vslide1down_##BITWIDTH. This bug is caught when run these instructions on qemu-riscv32. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230213094550.29621-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
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GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
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#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
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static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
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static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
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void *vs2, CPURISCVState *env, uint32_t desc) \
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{ \
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typedef uint##BITWIDTH##_t ETYPE; \
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@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
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GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
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#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
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static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
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static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
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void *vs2, CPURISCVState *env, uint32_t desc) \
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{ \
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typedef uint##BITWIDTH##_t ETYPE; \
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