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target/openrisc: Make coreid and numcores variable 

Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2017-06-18 01:50:06 +09:00
parent 0ca9fa2e3c
commit 8c949951ed
1 changed files with 3 additions and 2 deletions
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5
target/openrisc/sys_helper.c
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@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exception.h"
#include "sysemu/sysemu.h"
#define TO_SPR(group, number) (((group) << 11) + (number))
@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
return env->esr;
case TO_SPR(0, 128): /* COREID */
return 0;
return cpu->parent_obj.cpu_index;
case TO_SPR(0, 129): /* NUMCORES */
return 1;
return max_cpus;
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
idx = (spr - 1024);