target/openrisc: Make coreid and numcores variable
Previously coreid and numcores were hard coded as 0 and 1 respectively as OpenRISC QEMU did not have multicore support. Multicore support is now being added so these registers need to have configured values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -23,6 +23,7 @@
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "exception.h"
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#include "sysemu/sysemu.h"
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#define TO_SPR(group, number) (((group) << 11) + (number))
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@ -249,10 +250,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
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return env->esr;
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case TO_SPR(0, 128): /* COREID */
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return 0;
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return cpu->parent_obj.cpu_index;
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case TO_SPR(0, 129): /* NUMCORES */
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return 1;
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return max_cpus;
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case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
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idx = (spr - 1024);
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