target/xtensa updates:
- fix gdbstub register counts; - add big-endian core test_kc705_be; - convert to do_transaction_failed and add test for failed memory transactions; - fix couple FPU2000 bugs; - fix s32c1i implementation; - clean up exception handlers generation in xtensa tests; - add support for semihosting console input through a chardev. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAluhN3YTHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRITnD/9T5vId9XfKgByJF4pI3XFcfv6NUyTs 3sssBDZYd7rlEk0iLvlJBVA8qrx7Mgsl4Oz63I5AU0kT1GR1r0KjwcQbm/xom6pO /ct7bGGsRcap9182bhOvaFKG2iP2VobFcyRkmebY50ywzaYC/4g3LcUSo7mtuzzg RTzz2RKf1mwLitmh9dx7v6TRpztGK2JpZuyFAa/2zPc0H4VC4fQIqZt1AX/8bB18 +sZd2TBa+wS3q4ilNXeNXM1gHnQbJHNxDdQu0VUxDRk4HdYFsuQxrijyXJF8OiGa EQylgnQazrVsz2NX+dV8rB4/z+pn5m6V0+6dE3GVf+YTIJTKnt58dQZQrcOQX2IJ LgKPdEN7sXaHgpT4IC1gIr5m6nErBdqQtFSTjBWFw6Xj76c1l6u8Z/qZJx5wj1s2 95++Rja5pu15AiUYtlSyhZ1jD5zR8gxIsCdUVRJs2LArOC+tXATt+AflcceA7x6I 5mg+h12WUenGE0BhRaPBMtJjTRG4PscP55BtF5G7Jzz4K35Us0/I/eETe6Pazwt+ PNtWl/+HajSsvhYpm+dadOX0qzKIZNJe4jUV5GwJTRtMJxuTsBwdj8+Xs4/Pn+pD S4UrI4rr9NIgXfggiPbV9Wy6ybMYARwlr6Pi1JhJqzYf3aKgHrKjRqmO7j356Oxe TVEfV0kAwWoGCQ== =VPVK -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging target/xtensa updates: - fix gdbstub register counts; - add big-endian core test_kc705_be; - convert to do_transaction_failed and add test for failed memory transactions; - fix couple FPU2000 bugs; - fix s32c1i implementation; - clean up exception handlers generation in xtensa tests; - add support for semihosting console input through a chardev. # gpg: Signature made Tue 18 Sep 2018 18:35:50 BST # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180918-xtensa: target/xtensa: support input from chardev console target/xtensa: fix s32c1i TCGMemOp flags tests/tcg/xtensa: only generate defined exception handlers tests/tcg/xtensa: move exception handlers to separate section target/xtensa: fix FPU2000 bugs tests/tcg/xtensa: add test for failed memory transactions target/xtensa: convert to do_transaction_failed target/xtensa: add test_kc705_be core target/xtensa: clean up gdbstub register handling target/xtensa: fix gdbstub register counts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
8ca19bd882
|
|
@ -3,6 +3,7 @@ obj-y += core-dc233c.o
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|||
obj-y += core-de212.o
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obj-y += core-fsf.o
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obj-y += core-sample_controller.o
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obj-y += core-test_kc705_be.o
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obj-$(CONFIG_SOFTMMU) += monitor.o xtensa-semi.o
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obj-y += xtensa-isa.o
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obj-y += translate.o op_helper.o helper.o cpu.o
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|
|
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|||
|
|
@ -0,0 +1,52 @@
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|||
/*
|
||||
* Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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||||
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||||
#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include "core-test_kc705_be/core-isa.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_test_kc705_be
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#include "core-test_kc705_be/xtensa-modules.inc.c"
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static XtensaConfig test_kc705_be __attribute__((unused)) = {
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.name = "test_kc705_be",
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||||
.gdb_regmap = {
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||||
.reg = {
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||||
#include "core-test_kc705_be/gdb-config.inc.c"
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||||
}
|
||||
},
|
||||
.isa_internal = &xtensa_modules,
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||||
.clock_freq_khz = 40000,
|
||||
DEFAULT_SECTIONS
|
||||
};
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||||
|
||||
REGISTER_CORE(test_kc705_be)
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|
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@ -0,0 +1,575 @@
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|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
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||||
|
||||
Copyright (c) 1999-2015 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
|
||||
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 1 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2_MUL32X24 1 /* HiFi2 and 32x24 MACs */
|
||||
#define XCHAL_HAVE_HIFI2EP 1 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 1100002 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "test_kc705_be" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x00058D8C /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC1B3FFFF /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1C858D8C /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260002 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_2 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 8
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
/* Whether MEMCTL register has anything useful */
|
||||
#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \
|
||||
XCHAL_DCACHE_IS_COHERENT || \
|
||||
XCHAL_HAVE_ICACHE_DYN_WAYS || \
|
||||
XCHAL_HAVE_DCACHE_DYN_WAYS) && \
|
||||
(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 16 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000140
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00008000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00003000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F00BF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F01FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F0FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 2
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 5
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 4
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F0000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00008000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 15 /* profiling interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL4_NUM 15
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3, 5.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 5) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT16_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 15 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x00002340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00002340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2015 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,13, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 46,184,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 47,188, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
|
||||
"03:40:48:2b","03:40:48:7a",0,0,0,0)
|
||||
XTREG( 54,220,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
|
||||
"03:40:49:2b","03:40:49:7a",0,0,0,0)
|
||||
XTREG( 55,228,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
|
||||
"03:40:4a:2b","03:40:4a:7a",0,0,0,0)
|
||||
XTREG( 56,236,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
|
||||
"03:40:4b:2b","03:40:4b:7a",0,0,0,0)
|
||||
XTREG( 57,244,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
|
||||
"03:40:4c:2b","03:40:4c:7a",0,0,0,0)
|
||||
XTREG( 58,252,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
|
||||
"03:40:4d:2b","03:40:4d:7a",0,0,0,0)
|
||||
XTREG( 59,260,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
|
||||
"03:40:4e:2b","03:40:4e:7a",0,0,0,0)
|
||||
XTREG( 60,268,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
|
||||
"03:40:4f:2b","03:40:4f:7a",0,0,0,0)
|
||||
XTREG( 61,276,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
|
||||
"03:40:40:3c","03:40:40:1c",0,0,0,0)
|
||||
XTREG( 62,284,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
|
||||
"03:40:41:3c","03:40:44:1c",0,0,0,0)
|
||||
XTREG( 63,292,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
|
||||
"03:40:42:3c","03:40:48:1c",0,0,0,0)
|
||||
XTREG( 64,300,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
|
||||
"03:40:43:3c","03:40:4c:1c",0,0,0,0)
|
||||
XTREG( 65,308, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
|
||||
XTREG( 66,312,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
|
||||
XTREG( 67,316,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
|
||||
XTREG( 68,320,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
|
||||
XTREG( 69,324,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
|
||||
XTREG( 70,328,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
|
||||
XTREG( 71,332,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
|
||||
XTREG( 72,336,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 73,340,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
|
||||
XTREG( 74,344,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 75,348,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 76,352, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 77,356, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 78,360,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 79,364,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 80,368,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 81,372,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 82,376,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 83,380,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 84,384,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 85,388,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 86,392,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 87,396,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 88,400,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 89,404,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 90,408,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 91,412,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 92,416,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 93,420,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 94,424,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 95,428,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 96,432,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 97,436,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 98,440,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 99,444,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG(100,448,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG(101,452,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG(102,456,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG(103,460,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG(104,464,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG(105,468,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG(106,472, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG(107,476,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG(108,480,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG(109,484,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG(110,488,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG(112,496, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG(113,500,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG(114,504,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG(115,508,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG(116,512,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG(117,516, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(119,524,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(120,528,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(121,532,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(122,536,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(123,540,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(124,544,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG(125,548,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG(126,552,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(127,556,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(128,560,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(129,564,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(130,568,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(131,572,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(132,576,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(133,580,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(134,584,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(135,588,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(136,592,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(137,596,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(138,600,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(139,604,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(140,608, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(141,609, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(142,610, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(143,611, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(144,612, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(145,613, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(146,614, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(147,615, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(148,616, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(149,617, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(150,618, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(151,619, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(152,620, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(153,621, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(154,622, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(155,623, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(156,624, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(157,628, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(158,632, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(159,636, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG(160,640, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask20,0,0,0)
|
||||
XTREG(161,644, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask21,0,0,0)
|
||||
XTREG(162,648, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask22,0,0,0)
|
||||
XTREG(163,652,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask23,0,0,0)
|
||||
XTREG(164,660, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask24,0,0,0)
|
||||
XTREG(165,664, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid3,
|
||||
0,0,&xtensa_mask25,0,0,0)
|
||||
XTREG(166,668, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid2,
|
||||
0,0,&xtensa_mask26,0,0,0)
|
||||
XTREG(167,672, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid1,
|
||||
0,0,&xtensa_mask27,0,0,0)
|
||||
XTREG(168,676, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid6,
|
||||
0,0,&xtensa_mask28,0,0,0)
|
||||
XTREG(169,680, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid5,
|
||||
0,0,&xtensa_mask29,0,0,0)
|
||||
XTREG(170,684, 2, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid4,
|
||||
0,0,&xtensa_mask30,0,0,0)
|
||||
XTREG(171,688, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid6,
|
||||
0,0,&xtensa_mask31,0,0,0)
|
||||
XTREG(172,692, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid5,
|
||||
0,0,&xtensa_mask32,0,0,0)
|
||||
XTREG(173,696, 2, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid4,
|
||||
0,0,&xtensa_mask33,0,0,0)
|
||||
XTREG(174,700,10, 4, 4,0x201f,0x0006,-2, 6,0x1010,ptbase,
|
||||
0,0,&xtensa_mask34,0,0,0)
|
||||
XTREG(175,704, 1, 4, 4,0x2021,0x0006, 1, 5,0x1010,ae_overflow,
|
||||
0,0,&xtensa_mask35,0,0,0)
|
||||
XTREG(176,708, 6, 4, 4,0x2022,0x0006, 1, 5,0x1010,ae_sar,
|
||||
0,0,&xtensa_mask36,0,0,0)
|
||||
XTREG(177,712, 4, 4, 4,0x2023,0x0006, 1, 5,0x1010,ae_bitptr,
|
||||
0,0,&xtensa_mask37,0,0,0)
|
||||
XTREG(178,716, 4, 4, 4,0x2024,0x0006, 1, 5,0x1010,ae_bitsused,
|
||||
0,0,&xtensa_mask38,0,0,0)
|
||||
XTREG(179,720, 4, 4, 4,0x2025,0x0006, 1, 5,0x1010,ae_tablesize,
|
||||
0,0,&xtensa_mask39,0,0,0)
|
||||
XTREG(180,724, 4, 4, 4,0x2026,0x0006, 1, 5,0x1010,ae_first_ts,
|
||||
0,0,&xtensa_mask40,0,0,0)
|
||||
XTREG(181,728,27, 4, 4,0x2027,0x0006, 1, 5,0x1010,ae_nextoffset,
|
||||
0,0,&xtensa_mask41,0,0,0)
|
||||
XTREG_END
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
|
|||
#else
|
||||
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
|
||||
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
|
||||
cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
|
||||
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
|
||||
#endif
|
||||
cc->debug_excp_handler = xtensa_breakpoint_handler;
|
||||
cc->disas_set_info = xtensa_cpu_disas_set_info;
|
||||
|
|
|
|||
|
|
@ -497,12 +497,15 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
|
|||
int mmu_idx);
|
||||
void xtensa_cpu_do_interrupt(CPUState *cpu);
|
||||
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
|
||||
void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
|
||||
bool is_write, bool is_exec, int opaque,
|
||||
unsigned size);
|
||||
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
||||
unsigned size, MMUAccessType access_type,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr);
|
||||
void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
|
||||
fprintf_function cpu_fprintf, int flags);
|
||||
hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
void xtensa_count_regs(const XtensaConfig *config,
|
||||
unsigned *n_regs, unsigned *n_core_regs);
|
||||
int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||
int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||
void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
|
||||
|
|
|
|||
|
|
@ -23,6 +23,42 @@
|
|||
#include "exec/gdbstub.h"
|
||||
#include "qemu/log.h"
|
||||
|
||||
enum {
|
||||
xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
|
||||
xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
|
||||
xtRegisterTypeUserReg, /* User defined registers (rur). */
|
||||
xtRegisterTypeTieRegfile, /* User define register files. */
|
||||
xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
|
||||
xtRegisterTypeMapped, /* Mapped on Special Registers. */
|
||||
xtRegisterTypeUnmapped, /* Special case of masked registers. */
|
||||
xtRegisterTypeWindow, /* Live window registers (a0..a15). */
|
||||
xtRegisterTypeVirtual, /* PC, FP. */
|
||||
xtRegisterTypeUnknown
|
||||
};
|
||||
|
||||
#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
|
||||
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
|
||||
#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
|
||||
#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
|
||||
|
||||
void xtensa_count_regs(const XtensaConfig *config,
|
||||
unsigned *n_regs, unsigned *n_core_regs)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
|
||||
if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState &&
|
||||
config->gdb_regmap.reg[i].type != xtRegisterTypeMapped &&
|
||||
config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped) {
|
||||
++*n_regs;
|
||||
if ((config->gdb_regmap.reg[i].flags &
|
||||
XTENSA_REGISTER_FLAGS_PRIVILEGED) == 0) {
|
||||
++*n_core_regs;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
|
||||
{
|
||||
XtensaCPU *cpu = XTENSA_CPU(cs);
|
||||
|
|
@ -40,21 +76,21 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
}
|
||||
|
||||
switch (reg->type) {
|
||||
case 9: /*pc*/
|
||||
case xtRegisterTypeVirtual: /*pc*/
|
||||
return gdb_get_reg32(mem_buf, env->pc);
|
||||
|
||||
case 1: /*ar*/
|
||||
case xtRegisterTypeArRegfile: /*ar*/
|
||||
xtensa_sync_phys_from_window(env);
|
||||
return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
|
||||
% env->config->nareg]);
|
||||
|
||||
case 2: /*SR*/
|
||||
case xtRegisterTypeSpecialReg: /*SR*/
|
||||
return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
|
||||
|
||||
case 3: /*UR*/
|
||||
case xtRegisterTypeUserReg: /*UR*/
|
||||
return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
|
||||
|
||||
case 4: /*f*/
|
||||
case xtRegisterTypeTieRegfile: /*f*/
|
||||
i = reg->targno & 0x0f;
|
||||
switch (reg->size) {
|
||||
case 4:
|
||||
|
|
@ -69,7 +105,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
return reg->size;
|
||||
}
|
||||
|
||||
case 8: /*a*/
|
||||
case xtRegisterTypeWindow: /*a*/
|
||||
return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
|
||||
|
||||
default:
|
||||
|
|
@ -99,24 +135,24 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
tmp = ldl_p(mem_buf);
|
||||
|
||||
switch (reg->type) {
|
||||
case 9: /*pc*/
|
||||
case xtRegisterTypeVirtual: /*pc*/
|
||||
env->pc = tmp;
|
||||
break;
|
||||
|
||||
case 1: /*ar*/
|
||||
case xtRegisterTypeArRegfile: /*ar*/
|
||||
env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
|
||||
xtensa_sync_window_from_phys(env);
|
||||
break;
|
||||
|
||||
case 2: /*SR*/
|
||||
case xtRegisterTypeSpecialReg: /*SR*/
|
||||
env->sregs[reg->targno & 0xff] = tmp;
|
||||
break;
|
||||
|
||||
case 3: /*UR*/
|
||||
case xtRegisterTypeUserReg: /*UR*/
|
||||
env->uregs[reg->targno & 0xff] = tmp;
|
||||
break;
|
||||
|
||||
case 4: /*f*/
|
||||
case xtRegisterTypeTieRegfile: /*f*/
|
||||
switch (reg->size) {
|
||||
case 4:
|
||||
env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
|
||||
|
|
@ -130,7 +166,7 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
return reg->size;
|
||||
}
|
||||
|
||||
case 8: /*a*/
|
||||
case xtRegisterTypeWindow: /*a*/
|
||||
env->regs[reg->targno & 0x0f] = tmp;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -95,18 +95,10 @@ void xtensa_finalize_config(XtensaConfig *config)
|
|||
|
||||
if (config->gdb_regmap.num_regs == 0 ||
|
||||
config->gdb_regmap.num_core_regs == 0) {
|
||||
unsigned i;
|
||||
unsigned n_regs = 0;
|
||||
unsigned n_core_regs = 0;
|
||||
|
||||
for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
|
||||
if (config->gdb_regmap.reg[i].type != 6) {
|
||||
++n_regs;
|
||||
if ((config->gdb_regmap.reg[i].flags & 0x1) == 0) {
|
||||
++n_core_regs;
|
||||
}
|
||||
}
|
||||
}
|
||||
xtensa_count_regs(config, &n_regs, &n_core_regs);
|
||||
if (config->gdb_regmap.num_regs == 0) {
|
||||
config->gdb_regmap.num_regs = n_regs;
|
||||
}
|
||||
|
|
@ -574,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_write)
|
|||
}
|
||||
}
|
||||
|
||||
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
|
||||
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
|
||||
|
||||
static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
|
||||
uint32_t vaddr, int is_write, int mmu_idx,
|
||||
|
|
@ -592,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
|
|||
int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
|
||||
|
||||
if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
|
||||
may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
|
||||
may_lookup_pt && get_pte(env, vaddr, &pte)) {
|
||||
ring = (pte >> 4) & 0x3;
|
||||
wi = 0;
|
||||
split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
|
||||
|
|
@ -639,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
|
||||
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
|
||||
{
|
||||
CPUState *cs = CPU(xtensa_env_get_cpu(env));
|
||||
uint32_t paddr;
|
||||
|
|
@ -650,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
|
|||
int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
|
||||
&paddr, &page_size, &access, false);
|
||||
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
|
||||
__func__, vaddr, ret ? ~0 : paddr);
|
||||
if (ret == 0) {
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
|
||||
__func__, vaddr, pt_vaddr, paddr);
|
||||
} else {
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
|
||||
__func__, vaddr, pt_vaddr, ret);
|
||||
}
|
||||
|
||||
if (ret == 0) {
|
||||
*pte = ldl_phys(cs->as, paddr);
|
||||
MemTxResult result;
|
||||
|
||||
*pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
|
||||
&result);
|
||||
if (result != MEMTX_OK) {
|
||||
qemu_log_mask(CPU_LOG_MMU,
|
||||
"%s: couldn't load PTE: transaction failed (%u)\n",
|
||||
__func__, (unsigned)result);
|
||||
ret = 1;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
return ret == 0;
|
||||
}
|
||||
|
||||
static int get_physical_addr_region(CPUXtensaState *env,
|
||||
|
|
|
|||
|
|
@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
|
|||
}
|
||||
}
|
||||
|
||||
void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
|
||||
bool is_write, bool is_exec, int opaque,
|
||||
unsigned size)
|
||||
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
||||
unsigned size, MMUAccessType access_type,
|
||||
int mmu_idx, MemTxAttrs attrs,
|
||||
MemTxResult response, uintptr_t retaddr)
|
||||
{
|
||||
XtensaCPU *cpu = XTENSA_CPU(cs);
|
||||
CPUXtensaState *env = &cpu->env;
|
||||
|
||||
cpu_restore_state(cs, retaddr, true);
|
||||
HELPER(exception_cause_vaddr)(env, env->pc,
|
||||
is_exec ?
|
||||
access_type == MMU_INST_FETCH ?
|
||||
INSTR_PIF_ADDR_ERROR_CAUSE :
|
||||
LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
|
||||
is_exec ? addr : cs->mem_io_vaddr);
|
||||
addr);
|
||||
}
|
||||
|
||||
static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
|
||||
|
|
|
|||
|
|
@ -2288,7 +2288,7 @@ static void translate_s32c1i(DisasContext *dc, const uint32_t arg[],
|
|||
gen_load_store_alignment(dc, 2, addr, true);
|
||||
gen_check_atomctl(dc, addr);
|
||||
tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1],
|
||||
tmp, dc->cring, MO_32);
|
||||
tmp, dc->cring, MO_TEUL);
|
||||
tcg_temp_free(addr);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
|
|
@ -4706,7 +4706,7 @@ static void translate_movcond_s(DisasContext *dc, const uint32_t arg[],
|
|||
|
||||
tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]],
|
||||
cpu_R[arg[2]], zero,
|
||||
cpu_FR[arg[1]], cpu_FR[arg[2]]);
|
||||
cpu_FR[arg[1]], cpu_FR[arg[0]]);
|
||||
tcg_temp_free(zero);
|
||||
}
|
||||
}
|
||||
|
|
@ -4867,7 +4867,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
|
|||
.translate = translate_compare_s,
|
||||
.par = (const uint32_t[]){COMPARE_OLT},
|
||||
}, {
|
||||
.name = "rfr.s",
|
||||
.name = "rfr",
|
||||
.translate = translate_rfr_s,
|
||||
}, {
|
||||
.name = "round.s",
|
||||
|
|
@ -4921,7 +4921,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = {
|
|||
.translate = translate_ftoi_s,
|
||||
.par = (const uint32_t[]){float_round_to_zero, true},
|
||||
}, {
|
||||
.name = "wfr.s",
|
||||
.name = "wfr",
|
||||
.translate = translate_wfr_s,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -34,8 +34,6 @@
|
|||
#include "qemu/log.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
|
||||
static CharBackend *xtensa_sim_console;
|
||||
|
||||
enum {
|
||||
TARGET_SYS_exit = 1,
|
||||
TARGET_SYS_read = 3,
|
||||
|
|
@ -153,13 +151,48 @@ static uint32_t errno_h2g(int host_errno)
|
|||
}
|
||||
}
|
||||
|
||||
typedef struct XtensaSimConsole {
|
||||
CharBackend be;
|
||||
struct {
|
||||
char buffer[16];
|
||||
size_t offset;
|
||||
} input;
|
||||
} XtensaSimConsole;
|
||||
|
||||
static XtensaSimConsole *sim_console;
|
||||
|
||||
static IOCanReadHandler sim_console_can_read;
|
||||
static int sim_console_can_read(void *opaque)
|
||||
{
|
||||
XtensaSimConsole *p = opaque;
|
||||
|
||||
return sizeof(p->input.buffer) - p->input.offset;
|
||||
}
|
||||
|
||||
static IOReadHandler sim_console_read;
|
||||
static void sim_console_read(void *opaque, const uint8_t *buf, int size)
|
||||
{
|
||||
XtensaSimConsole *p = opaque;
|
||||
size_t copy = sizeof(p->input.buffer) - p->input.offset;
|
||||
|
||||
if (size < copy) {
|
||||
copy = size;
|
||||
}
|
||||
memcpy(p->input.buffer + p->input.offset, buf, copy);
|
||||
p->input.offset += copy;
|
||||
}
|
||||
|
||||
void xtensa_sim_open_console(Chardev *chr)
|
||||
{
|
||||
static CharBackend console;
|
||||
static XtensaSimConsole console;
|
||||
|
||||
qemu_chr_fe_init(&console, chr, &error_abort);
|
||||
qemu_chr_fe_set_handlers(&console, NULL, NULL, NULL, NULL, NULL, NULL, true);
|
||||
xtensa_sim_console = &console;
|
||||
qemu_chr_fe_init(&console.be, chr, &error_abort);
|
||||
qemu_chr_fe_set_handlers(&console.be,
|
||||
sim_console_can_read,
|
||||
sim_console_read,
|
||||
NULL, NULL, &console,
|
||||
NULL, true);
|
||||
sim_console = &console;
|
||||
}
|
||||
|
||||
void HELPER(simcall)(CPUXtensaState *env)
|
||||
|
|
@ -195,11 +228,27 @@ void HELPER(simcall)(CPUXtensaState *env)
|
|||
if (buf) {
|
||||
vaddr += io_sz;
|
||||
len -= io_sz;
|
||||
if (fd < 3 && xtensa_sim_console) {
|
||||
if (fd < 3 && sim_console) {
|
||||
if (is_write && (fd == 1 || fd == 2)) {
|
||||
io_done = qemu_chr_fe_write_all(xtensa_sim_console,
|
||||
io_done = qemu_chr_fe_write_all(&sim_console->be,
|
||||
buf, io_sz);
|
||||
regs[3] = errno_h2g(errno);
|
||||
} else if (!is_write && fd == 0) {
|
||||
if (sim_console->input.offset) {
|
||||
io_done = sim_console->input.offset;
|
||||
if (io_sz < io_done) {
|
||||
io_done = io_sz;
|
||||
}
|
||||
memcpy(buf, sim_console->input.buffer, io_done);
|
||||
memmove(sim_console->input.buffer,
|
||||
sim_console->input.buffer + io_done,
|
||||
sim_console->input.offset - io_done);
|
||||
sim_console->input.offset -= io_done;
|
||||
qemu_chr_fe_accept_input(&sim_console->be);
|
||||
} else {
|
||||
io_done = -1;
|
||||
regs[3] = TARGET_EAGAIN;
|
||||
}
|
||||
} else {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"%s fd %d is not supported with chardev console\n",
|
||||
|
|
@ -292,9 +341,11 @@ void HELPER(simcall)(CPUXtensaState *env)
|
|||
tv.tv_sec = (int32_t)tswap32(target_tvv[0]);
|
||||
tv.tv_usec = (int32_t)tswap32(target_tvv[1]);
|
||||
}
|
||||
if (fd < 3 && xtensa_sim_console) {
|
||||
if (fd < 3 && sim_console) {
|
||||
if ((fd == 1 || fd == 2) && rq == SELECT_ONE_WRITE) {
|
||||
regs[2] = 1;
|
||||
} else if (fd == 0 && rq == SELECT_ONE_READ) {
|
||||
regs[2] = sim_console->input.offset > 0;
|
||||
} else {
|
||||
regs[2] = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ TESTCASES += test_mmu.tst
|
|||
TESTCASES += test_mul16.tst
|
||||
TESTCASES += test_mul32.tst
|
||||
TESTCASES += test_nsa.tst
|
||||
TESTCASES += test_phys_mem.tst
|
||||
ifdef XT
|
||||
TESTCASES += test_pipeline.tst
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -24,64 +24,71 @@ SECTIONS
|
|||
|
||||
.vector :
|
||||
{
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
. = XCHAL_WINDOW_OF4_VECOFS;
|
||||
*(.vector.window_overflow_4)
|
||||
*(.vector.window_overflow_4.*)
|
||||
. = XCHAL_WINDOW_UF4_VECOFS;
|
||||
*(.vector.window_underflow_4)
|
||||
*(.vector.window_underflow_4.*)
|
||||
. = XCHAL_WINDOW_OF8_VECOFS;
|
||||
*(.vector.window_overflow_8)
|
||||
*(.vector.window_overflow_8.*)
|
||||
. = XCHAL_WINDOW_UF8_VECOFS;
|
||||
*(.vector.window_underflow_8)
|
||||
*(.vector.window_underflow_8.*)
|
||||
. = XCHAL_WINDOW_OF12_VECOFS;
|
||||
*(.vector.window_overflow_12)
|
||||
*(.vector.window_overflow_12.*)
|
||||
. = XCHAL_WINDOW_UF12_VECOFS;
|
||||
*(.vector.window_underflow_12)
|
||||
*(.vector.window_underflow_12.*)
|
||||
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
|
||||
. = XCHAL_INTLEVEL2_VECOFS;
|
||||
*(.vector.level2)
|
||||
*(.vector.level2.*)
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
|
||||
. = XCHAL_INTLEVEL3_VECOFS;
|
||||
*(.vector.level3)
|
||||
*(.vector.level3.*)
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
|
||||
. = XCHAL_INTLEVEL4_VECOFS;
|
||||
*(.vector.level4)
|
||||
*(.vector.level4.*)
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
|
||||
. = XCHAL_INTLEVEL5_VECOFS;
|
||||
*(.vector.level5)
|
||||
*(.vector.level5.*)
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
|
||||
. = XCHAL_INTLEVEL6_VECOFS;
|
||||
*(.vector.level6)
|
||||
*(.vector.level6.*)
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
|
||||
. = XCHAL_INTLEVEL7_VECOFS;
|
||||
*(.vector.level7)
|
||||
*(.vector.level7.*)
|
||||
#endif
|
||||
|
||||
. = XCHAL_KERNEL_VECOFS;
|
||||
*(.vector.kernel)
|
||||
*(.vector.kernel.*)
|
||||
. = XCHAL_USER_VECOFS;
|
||||
*(.vector.user)
|
||||
*(.vector.user.*)
|
||||
. = XCHAL_DOUBLEEXC_VECOFS;
|
||||
*(.vector.double)
|
||||
} > ram
|
||||
|
||||
.vector.text :
|
||||
{
|
||||
*(.vector.window_overflow_4.*)
|
||||
*(.vector.window_underflow_4.*)
|
||||
*(.vector.window_overflow_8.*)
|
||||
*(.vector.window_underflow_8.*)
|
||||
*(.vector.window_overflow_12.*)
|
||||
*(.vector.window_underflow_12.*)
|
||||
|
||||
*(.vector.level2.*)
|
||||
*(.vector.level3.*)
|
||||
*(.vector.level4.*)
|
||||
*(.vector.level5.*)
|
||||
*(.vector.level6.*)
|
||||
*(.vector.level7.*)
|
||||
|
||||
*(.vector.kernel.*)
|
||||
*(.vector.user.*)
|
||||
*(.vector.double.*)
|
||||
} > ram
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
#include "macros.inc"
|
||||
|
||||
test_suite phys_mem
|
||||
|
||||
.purgem test_init
|
||||
|
||||
.macro test_init
|
||||
movi a2, 0xc0000003 /* PPN */
|
||||
movi a3, 0xc0000004 /* VPN */
|
||||
wdtlb a2, a3
|
||||
witlb a2, a3
|
||||
movi a2, 0xc0000000
|
||||
wsr a2, ptevaddr
|
||||
.endm
|
||||
|
||||
test inst_fetch_get_pte_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0x20000000
|
||||
jx a2
|
||||
2:
|
||||
movi a2, 0x20000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 16
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test read_get_pte_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0x20000000
|
||||
1:
|
||||
l32i a3, a2, 0
|
||||
test_fail
|
||||
2:
|
||||
movi a2, 0x20000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
movi a2, 1b
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 24
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test write_get_pte_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0x20000000
|
||||
1:
|
||||
s32i a3, a2, 0
|
||||
test_fail
|
||||
2:
|
||||
movi a2, 0x20000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
movi a2, 1b
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 24
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test inst_fetch_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0xc0000000
|
||||
jx a2
|
||||
2:
|
||||
movi a2, 0xc0000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 14
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test read_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0xc0000000
|
||||
1:
|
||||
l32i a3, a2, 0
|
||||
test_fail
|
||||
2:
|
||||
movi a2, 0xc0000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
movi a2, 1b
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 15
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test write_no_phys
|
||||
set_vector kernel, 2f
|
||||
|
||||
movi a2, 0xc0000000
|
||||
1:
|
||||
s32i a3, a2, 0
|
||||
test_fail
|
||||
2:
|
||||
movi a2, 0xc0000000
|
||||
rsr a3, excvaddr
|
||||
assert eq, a2, a3
|
||||
movi a2, 1b
|
||||
rsr a3, epc1
|
||||
assert eq, a2, a3
|
||||
rsr a3, exccause
|
||||
movi a2, 15
|
||||
assert eq, a2, a3
|
||||
test_end
|
||||
|
||||
test_suite_end
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
#include "core-isa.h"
|
||||
|
||||
.macro vector name
|
||||
|
||||
.section .vector.\name
|
||||
|
|
@ -20,19 +22,33 @@ handler_\name\(): .word 0
|
|||
|
||||
.endm
|
||||
|
||||
#if XCHAL_HAVE_WINDOWED
|
||||
vector window_overflow_4
|
||||
vector window_overflow_8
|
||||
vector window_overflow_12
|
||||
vector window_underflow_4
|
||||
vector window_underflow_8
|
||||
vector window_underflow_12
|
||||
#endif
|
||||
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
|
||||
vector level2
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
|
||||
vector level3
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
|
||||
vector level4
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
|
||||
vector level5
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
|
||||
vector level6
|
||||
#endif
|
||||
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
|
||||
vector level7
|
||||
#endif
|
||||
|
||||
vector kernel
|
||||
vector user
|
||||
|
|
|
|||
Loading…
Reference in New Issue