From 8d162c2b68db72623a507069fda0e35ccd1c6b85 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 19 Nov 2007 16:10:33 +0000
Subject: [PATCH] Add older 4Km variants.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3708 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/translate_init.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index f6bda53fec..6a4c435768 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -100,6 +100,23 @@ static mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x1278FF17,
         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
     },
+    {
+        .name = "4Km",
+        .CP0_PRid = 0x00018300,
+        /* Config1 implemented, fixed mapping MMU,
+           no virtual icache, uncached coherency. */
+        .CP0_Config0 = (1 << CP0C0_M) |
+                    (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
+        .CP0_Config1 = MIPS_CONFIG1 |
+		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+    },
     {
         .name = "4KEcR1",
         .CP0_PRid = 0x00018400,
@@ -114,6 +131,23 @@ static mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x1278FF17,
         .insn_flags = CPU_MIPS32 | ASE_MIPS16,
     },
+    {
+        .name = "4KEmR1",
+        .CP0_PRid = 0x00018500,
+        /* Config1 implemented, fixed mapping MMU,
+           no virtual icache, uncached coherency. */
+        .CP0_Config0 = (1 << CP0C0_M) |
+                    (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0),
+        .CP0_Config1 = MIPS_CONFIG1 |
+		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+        .CP0_Config2 = MIPS_CONFIG2,
+        .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x1258FF17,
+        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
+    },
     {
         .name = "4KEc",
         .CP0_PRid = 0x00019000,