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target-arm: Prepare cpreg writefns/readfns for EL3/SecExt 

This patch changes some readfns/writefns to use raw_write
and raw_read functions, which use the fieldoffset specified
in ARMCPRegInfo instead of directly accessing the field.
This will simplify patches for EL3 & Security Extensions.

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Message-id: 1401962428-14749-1-git-send-email-aggelerf@ethz.ch
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Fabian Aggeler 2014-06-09 15:43:22 +01:00 committed by Peter Maydell
parent bf01601764
commit 8d5c773e32
1 changed files with 14 additions and 14 deletions
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28
target-arm/helper.c
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@ -319,7 +319,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{ {
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
env->cp15.c3 = value; raw_write(env, ri, value);
tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */ tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
} }
@ -327,12 +327,12 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{ {
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.c13_fcse != value) { if (raw_read(env, ri) != value) {
/* Unlike real hardware the qemu TLB uses virtual addresses, /* Unlike real hardware the qemu TLB uses virtual addresses,
* not modified virtual addresses, so this causes a TLB flush. * not modified virtual addresses, so this causes a TLB flush.
*/ */
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);
env->cp15.c13_fcse = value; raw_write(env, ri, value);
} }
} }
@ -341,7 +341,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU) if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
&& !extended_addresses_enabled(env)) { && !extended_addresses_enabled(env)) {
/* For VMSA (when not using the LPAE long descriptor page table /* For VMSA (when not using the LPAE long descriptor page table
* format) this register includes the ASID, so do a TLB flush. * format) this register includes the ASID, so do a TLB flush.
@ -349,7 +349,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
*/ */
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);
} }
env->cp15.contextidr_el1 = value; raw_write(env, ri, value);
} }
static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -693,7 +693,7 @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
env->cp15.c0_cssel = value & 0xf; raw_write(env, ri, value & 0xf);
} }
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@ -1216,11 +1216,11 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{ {
if (arm_feature(env, ARM_FEATURE_LPAE)) { if (arm_feature(env, ARM_FEATURE_LPAE)) {
env->cp15.par_el1 = value; raw_write(env, ri, value);
} else if (arm_feature(env, ARM_FEATURE_V7)) { } else if (arm_feature(env, ARM_FEATURE_V7)) {
env->cp15.par_el1 = value & 0xfffff6ff; raw_write(env, ri, value & 0xfffff6ff);
} else { } else {
env->cp15.par_el1 = value & 0xfffff1ff; raw_write(env, ri, value & 0xfffff1ff);
} }
} }
@ -1423,7 +1423,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
* for long-descriptor tables the TTBCR fields are used differently * for long-descriptor tables the TTBCR fields are used differently
* and the c2_mask and c2_base_mask values are meaningless. * and the c2_mask and c2_base_mask values are meaningless.
*/ */
env->cp15.c2_control = value; raw_write(env, ri, value);
env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
} }
@ -1445,7 +1445,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
env->cp15.c2_base_mask = 0xffffc000u; env->cp15.c2_base_mask = 0xffffc000u;
env->cp15.c2_control = 0; raw_write(env, ri, 0);
env->cp15.c2_mask = 0; env->cp15.c2_mask = 0;
} }
@ -1456,7 +1456,7 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);
env->cp15.c2_control = value; raw_write(env, ri, value);
} }
static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2151,14 +2151,14 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.c1_sys == value) { if (raw_read(env, ri) == value) {
/* Skip the TLB flush if nothing actually changed; Linux likes /* Skip the TLB flush if nothing actually changed; Linux likes
* to do a lot of pointless SCTLR writes. * to do a lot of pointless SCTLR writes.
*/ */
return; return;
} }
env->cp15.c1_sys = value; raw_write(env, ri, value);
/* ??? Lots of these bits are not implemented. */ /* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */ /* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);