hw/timer/imx_epit: fix compare timer handling
- fix #1263 for CR writes - rework compare time handling - The compare timer has to run even if CR.OCIEN is not set, as SR.OCIF must be updated. - The compare timer fires exactly once when the compare value is less than the current value, but the reload values is less than the compare value. - The compare timer will never fire if the reload value is less than the compare value. Disable it in this case. Signed-off-by: Axel Heider <axel.heider@hensoldt.net> [PMM: fixed minor style nits] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -6,6 +6,7 @@
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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* Updated by Axel Heider
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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@ -151,33 +152,126 @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
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return reg_value;
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}
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/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
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static void imx_epit_reload_compare_timer(IMXEPITState *s)
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/*
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* Must be called from a ptimer_transaction_begin/commit block for
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* s->timer_cmp, but outside of a transaction block of s->timer_reload,
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* so the proper counter value is read.
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*/
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static void imx_epit_update_compare_timer(IMXEPITState *s)
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{
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if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
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/* if the compare feature is on and timers are running */
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uint32_t tmp = ptimer_get_count(s->timer_reload);
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uint64_t next;
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if (tmp > s->cmp) {
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/* It'll fire in this round of the timer */
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next = tmp - s->cmp;
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} else { /* catch it next time around */
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next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
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uint64_t counter = 0;
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bool is_oneshot = false;
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/*
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* The compare timer only has to run if the timer peripheral is active
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* and there is an input clock, Otherwise it can be switched off.
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*/
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bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
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if (is_active) {
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/*
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* Calculate next timeout for compare timer. Reading the reload
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* counter returns proper results only if pending transactions
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* on it are committed here. Otherwise stale values are be read.
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*/
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counter = ptimer_get_count(s->timer_reload);
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uint64_t limit = ptimer_get_limit(s->timer_cmp);
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/*
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* The compare timer is a periodic timer if the limit is at least
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* the compare value. Otherwise it may fire at most once in the
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* current round.
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*/
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bool is_oneshot = (limit >= s->cmp);
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if (counter >= s->cmp) {
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/* The compare timer fires in the current round. */
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counter -= s->cmp;
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} else if (!is_oneshot) {
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/*
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* The compare timer fires after a reload, as it is below the
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* compare value already in this round. Note that the counter
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* value calculated below can be above the 32-bit limit, which
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* is legal here because the compare timer is an internal
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* helper ptimer only.
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*/
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counter += limit - s->cmp;
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} else {
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/*
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* The compare timer won't fire in this round, and the limit is
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* set to a value below the compare value. This practically means
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* it will never fire, so it can be switched off.
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*/
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is_active = false;
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}
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ptimer_set_count(s->timer_cmp, next);
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}
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/*
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* Set the compare timer and let it run, or stop it. This is agnostic
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* of CR.OCIEN bit, as this bit affects interrupt generation only. The
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* compare timer needs to run even if no interrupts are to be generated,
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* because the SR.OCIF bit must be updated also.
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* Note that the timer might already be stopped or be running with
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* counter values. However, finding out when an update is needed and
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* when not is not trivial. It's much easier applying the setting again,
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* as this does not harm either and the overhead is negligible.
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*/
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if (is_active) {
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ptimer_set_count(s->timer_cmp, counter);
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ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
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} else {
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ptimer_stop(s->timer_cmp);
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}
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}
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static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
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{
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uint32_t freq = 0;
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uint32_t oldcr = s->cr;
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s->cr = value & 0x03ffffff;
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if (s->cr & CR_SWR) {
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/* handle the reset */
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/*
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* Reset clears CR.SWR again. It does not touch CR.EN, but the timers
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* are still stopped because the input clock is disabled.
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*/
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imx_epit_reset(s, false);
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} else {
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uint32_t freq;
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uint32_t toggled_cr_bits = oldcr ^ s->cr;
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/* re-initialize the limits if CR.RLD has changed */
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bool set_limit = toggled_cr_bits & CR_RLD;
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/* set the counter if the timer got just enabled and CR.ENMOD is set */
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bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
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bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
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ptimer_transaction_begin(s->timer_cmp);
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ptimer_transaction_begin(s->timer_reload);
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freq = imx_epit_get_freq(s);
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if (freq) {
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ptimer_set_freq(s->timer_reload, freq);
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ptimer_set_freq(s->timer_cmp, freq);
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}
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if (set_limit || set_counter) {
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uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
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ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
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if (set_limit) {
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ptimer_set_limit(s->timer_cmp, limit, 0);
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}
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}
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/*
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* If there is an input clock and the peripheral is enabled, then
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* ensure the wall clock timer is ticking. Otherwise stop the timers.
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* The compare timer will be updated later.
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*/
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if (freq && (s->cr & CR_EN)) {
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ptimer_run(s->timer_reload, 0);
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} else {
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ptimer_stop(s->timer_reload);
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}
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/* Commit changes to reload timer, so they can propagate. */
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ptimer_transaction_commit(s->timer_reload);
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/* Update compare timer based on the committed reload timer value. */
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imx_epit_update_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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}
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/*
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@ -186,60 +280,6 @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
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* - write to CR.EN or CR.OCIE
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*/
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imx_epit_update_int(s);
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/*
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* TODO: could we 'break' here for reset? following operations appear
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* to duplicate the work imx_epit_reset() already did.
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*/
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ptimer_transaction_begin(s->timer_cmp);
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ptimer_transaction_begin(s->timer_reload);
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/*
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* Update the frequency. In case of a reset the input clock was
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* switched off, so this can be skipped.
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*/
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if (!(s->cr & CR_SWR)) {
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freq = imx_epit_get_freq(s);
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if (freq) {
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ptimer_set_freq(s->timer_reload, freq);
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ptimer_set_freq(s->timer_cmp, freq);
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}
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}
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if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
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if (s->cr & CR_ENMOD) {
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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ptimer_set_limit(s->timer_cmp, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
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ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
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}
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}
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imx_epit_reload_compare_timer(s);
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ptimer_run(s->timer_reload, 0);
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if (s->cr & CR_OCIEN) {
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ptimer_run(s->timer_cmp, 0);
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} else {
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ptimer_stop(s->timer_cmp);
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}
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} else if (!(s->cr & CR_EN)) {
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/* stop both timers */
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ptimer_stop(s->timer_reload);
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ptimer_stop(s->timer_cmp);
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} else if (s->cr & CR_OCIEN) {
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if (!(oldcr & CR_OCIEN)) {
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imx_epit_reload_compare_timer(s);
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ptimer_run(s->timer_cmp, 0);
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}
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} else {
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ptimer_stop(s->timer_cmp);
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}
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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}
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static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
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@ -266,14 +306,10 @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
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/* If IOVW bit is set then set the timer value */
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ptimer_set_count(s->timer_reload, s->lr);
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}
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/*
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* Commit the change to s->timer_reload, so it can propagate. Otherwise
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* the timer interrupt may not fire properly. The commit must happen
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* before calling imx_epit_reload_compare_timer(), which reads
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* s->timer_reload internally again.
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*/
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/* Commit the changes to s->timer_reload, so they can propagate. */
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ptimer_transaction_commit(s->timer_reload);
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imx_epit_reload_compare_timer(s);
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/* Update the compare timer based on the committed reload timer value. */
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imx_epit_update_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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}
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@ -281,8 +317,9 @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
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{
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s->cmp = value;
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/* Update the compare timer based on the committed reload timer value. */
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ptimer_transaction_begin(s->timer_cmp);
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imx_epit_reload_compare_timer(s);
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imx_epit_update_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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}
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@ -322,6 +359,9 @@ static void imx_epit_cmp(void *opaque)
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{
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IMXEPITState *s = IMX_EPIT(opaque);
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/* The cmp ptimer can't be running when the peripheral is disabled */
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assert(s->cr & CR_EN);
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DPRINTF("sr was %d\n", s->sr);
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/* Set interrupt status bit SR.OCIF and update the interrupt state */
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s->sr |= SR_OCIF;
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