linux-user/aarch64: Pass syndrome to EXC_*_ABORT
A proper syndrome is required to fill in the proper si_code. Use page_get_flags to determine permission vs translation for user-only. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210212184902.1251044-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -23,6 +23,7 @@
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#include "cpu_loop-common.h"
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#include "qemu/guest-random.h"
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#include "hw/semihosting/common-semi.h"
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#include "target/arm/syndrome.h"
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#define get_user_code_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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@ -76,7 +77,7 @@
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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int trapnr, ec, fsc;
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abi_long ret;
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target_siginfo_t info;
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@ -117,9 +118,26 @@ void cpu_loop(CPUARMState *env)
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case EXCP_DATA_ABORT:
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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/* XXX: check env->error_code */
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->exception.vaddress;
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/* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
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ec = syn_get_ec(env->exception.syndrome);
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assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
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/* Both EC have the same format for FSC, or close enough. */
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fsc = extract32(env->exception.syndrome, 0, 6);
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switch (fsc) {
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case 0x04 ... 0x07: /* Translation fault, level {0-3} */
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info.si_code = TARGET_SEGV_MAPERR;
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break;
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case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
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case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
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info.si_code = TARGET_SEGV_ACCERR;
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break;
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default:
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g_assert_not_reached();
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}
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_DEBUG:
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@ -154,21 +154,24 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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bool probe, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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ARMMMUFaultInfo fi = {};
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#ifdef CONFIG_USER_ONLY
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cpu->env.exception.vaddress = address;
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = EXCP_PREFETCH_ABORT;
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int flags = page_get_flags(useronly_clean_ptr(address));
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if (flags & PAGE_VALID) {
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fi.type = ARMFault_Permission;
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} else {
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cs->exception_index = EXCP_DATA_ABORT;
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fi.type = ARMFault_Translation;
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}
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cpu_loop_exit_restore(cs, retaddr);
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
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#else
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hwaddr phys_addr;
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target_ulong page_size;
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int prot, ret;
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MemTxAttrs attrs = {};
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ARMMMUFaultInfo fi = {};
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ARMCacheAttrs cacheattrs = {};
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/*
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