aspeed/sdmc: Introduce an object class per SoC
Use class handlers and class constants to differentiate the characteristics of the memory controller and remove the 'silicon_rev' property. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -205,10 +205,9 @@ static void aspeed_soc_init(Object *obj)
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sizeof(s->spi[i]), typename);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
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TYPE_ASPEED_SDMC);
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qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
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sc->info->silicon_rev);
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typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size", &error_abort);
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object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
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@ -110,6 +110,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSDMCState *s = ASPEED_SDMC(opaque);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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addr >>= 2;
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@ -130,41 +131,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
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return;
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}
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if (addr == R_CONF) {
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/* Make sure readonly bits are kept */
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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data &= ~ASPEED_SDMC_READONLY_MASK;
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data |= s->fixed_conf;
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
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data |= s->fixed_conf;
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (s->silicon_rev == AST2500_A0_SILICON_REV ||
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s->silicon_rev == AST2500_A1_SILICON_REV) {
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switch (addr) {
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case R_STATUS1:
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/* Will never return 'busy' */
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data &= ~PHY_BUSY_STATE;
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break;
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case R_ECC_TEST_CTRL:
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/* Always done, always happy */
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data |= ECC_TEST_FINISHED;
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data &= ~ECC_TEST_FAIL;
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break;
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default:
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break;
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}
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}
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s->regs[addr] = data;
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asc->write(s, addr, data);
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}
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static const MemoryRegionOps aspeed_sdmc_ops = {
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@ -222,44 +189,21 @@ static int ast2500_rambits(AspeedSDMCState *s)
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static void aspeed_sdmc_reset(DeviceState *dev)
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{
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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memset(s->regs, 0, sizeof(s->regs));
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/* Set ram size bit and defaults values */
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s->regs[R_CONF] = s->fixed_conf;
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s->regs[R_CONF] = asc->compute_conf(s, 0);
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}
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static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSDMCState *s = ASPEED_SDMC(dev);
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AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
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if (!is_supported_silicon_rev(s->silicon_rev)) {
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error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
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s->silicon_rev);
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return;
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}
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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case AST2400_A1_SILICON_REV:
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s->ram_bits = ast2400_rambits(s);
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s->max_ram_size = 512 << 20;
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s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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break;
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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s->ram_bits = ast2500_rambits(s);
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s->max_ram_size = 1024 << 20;
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s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_CACHE_INITIAL_DONE |
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ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
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break;
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default:
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g_assert_not_reached();
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}
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s->max_ram_size = asc->max_ram_size;
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
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TYPE_ASPEED_SDMC, 0x1000);
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@ -277,7 +221,6 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
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};
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static Property aspeed_sdmc_properties[] = {
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DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
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DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
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DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
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DEFINE_PROP_END_OF_LIST(),
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@ -298,11 +241,110 @@ static const TypeInfo aspeed_sdmc_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSDMCState),
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.class_init = aspeed_sdmc_class_init,
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.class_size = sizeof(AspeedSDMCClass),
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.abstract = true,
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};
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static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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{
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uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
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ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
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/* Make sure readonly bits are kept */
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data &= ~ASPEED_SDMC_READONLY_MASK;
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return data | fixed_conf;
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}
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static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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switch (reg) {
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case R_CONF:
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data = aspeed_2400_sdmc_compute_conf(s, data);
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break;
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default:
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break;
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}
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s->regs[reg] = data;
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}
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static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
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dc->desc = "ASPEED 2400 SDRAM Memory Controller";
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asc->max_ram_size = 512 << 20;
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asc->compute_conf = aspeed_2400_sdmc_compute_conf;
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asc->write = aspeed_2400_sdmc_write;
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}
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static const TypeInfo aspeed_2400_sdmc_info = {
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.name = TYPE_ASPEED_2400_SDMC,
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.parent = TYPE_ASPEED_SDMC,
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.class_init = aspeed_2400_sdmc_class_init,
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};
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static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
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{
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uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
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ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
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ASPEED_SDMC_CACHE_INITIAL_DONE |
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ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
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/* Make sure readonly bits are kept */
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data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
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return data | fixed_conf;
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}
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static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
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uint32_t data)
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{
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switch (reg) {
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case R_CONF:
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data = aspeed_2500_sdmc_compute_conf(s, data);
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break;
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case R_STATUS1:
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/* Will never return 'busy' */
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data &= ~PHY_BUSY_STATE;
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break;
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case R_ECC_TEST_CTRL:
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/* Always done, always happy */
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data |= ECC_TEST_FINISHED;
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data &= ~ECC_TEST_FAIL;
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break;
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default:
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break;
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}
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s->regs[reg] = data;
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}
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static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
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dc->desc = "ASPEED 2500 SDRAM Memory Controller";
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asc->max_ram_size = 1024 << 20;
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asc->compute_conf = aspeed_2500_sdmc_compute_conf;
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asc->write = aspeed_2500_sdmc_write;
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}
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static const TypeInfo aspeed_2500_sdmc_info = {
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.name = TYPE_ASPEED_2500_SDMC,
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.parent = TYPE_ASPEED_SDMC,
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.class_init = aspeed_2500_sdmc_class_init,
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};
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static void aspeed_sdmc_register_types(void)
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{
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type_register_static(&aspeed_sdmc_info);
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type_register_static(&aspeed_2400_sdmc_info);
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type_register_static(&aspeed_2500_sdmc_info);
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}
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type_init(aspeed_sdmc_register_types);
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@ -13,6 +13,8 @@
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#define TYPE_ASPEED_SDMC "aspeed.sdmc"
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#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
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#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
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#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
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#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
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@ -24,12 +26,21 @@ typedef struct AspeedSDMCState {
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MemoryRegion iomem;
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uint32_t regs[ASPEED_SDMC_NR_REGS];
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uint32_t silicon_rev;
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uint32_t ram_bits;
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uint64_t ram_size;
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uint64_t max_ram_size;
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uint32_t fixed_conf;
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} AspeedSDMCState;
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#define ASPEED_SDMC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC)
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#define ASPEED_SDMC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC)
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typedef struct AspeedSDMCClass {
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SysBusDeviceClass parent_class;
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uint64_t max_ram_size;
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uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
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void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
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} AspeedSDMCClass;
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#endif /* ASPEED_SDMC_H */
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