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target/mips: add or remove space to fix checkpatch errors

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Add or remove space to fix errors issued by checkpatch.pl tool
"ERROR: spaces required around that..."
"ERROR: space required after that..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that..."
"ERROR: space prohibited between function name and open parenthesis"
"ERROR: code indent should never use tabs"
"ERROR: line over 90 characters"
within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>
This commit is contained in:
Jules Irenge 2019-04-13 21:28:17 +01:00 committed by Aleksandar Markovic
parent 86e636951d
commit 8ebf2e1a68
1 changed files with 94 additions and 81 deletions
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175
target/mips/cpu.h
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@ -22,10 +22,10 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
typedef union wr_t wr_t;
union wr_t {
int8_t b[MSA_WRLEN/8];
int16_t h[MSA_WRLEN/16];
int32_t w[MSA_WRLEN/32];
int64_t d[MSA_WRLEN/64];
int8_t b[MSA_WRLEN / 8];
int16_t h[MSA_WRLEN / 16];
int32_t w[MSA_WRLEN / 32];
int64_t d[MSA_WRLEN / 64];
};
typedef union fpr_t fpr_t;
@ -71,16 +71,29 @@ struct CPUMIPSFPUContext {
#define FCR31_FS 24
#define FCR31_ABS2008 19
#define FCR31_NAN2008 18
#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
#define SET_FP_COND(num, env) do { ((env).fcr31) |= \
((num) ? (1 << ((num) + 24)) : \
(1 << 23)); \
} while (0)
#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
~((num) ? (1 << ((num) + 24)) : \
(1 << 23)); \
} while (0)
#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
(((env).fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
#define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
((v & 0x3f) << 12); \
} while (0)
#define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
((v & 0x1f) << 7); \
} while (0)
#define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
((v & 0x1f) << 2); \
} while (0)
#define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
#define FP_INEXACT 1
#define FP_UNDERFLOW 2
#define FP_OVERFLOW 4
@ -95,25 +108,25 @@ struct CPUMIPSFPUContext {
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
int32_t CP0_MVPControl;
#define CP0MVPCo_CPA 3
#define CP0MVPCo_STLB 2
#define CP0MVPCo_VPC 1
#define CP0MVPCo_EVP 0
#define CP0MVPCo_CPA 3
#define CP0MVPCo_STLB 2
#define CP0MVPCo_VPC 1
#define CP0MVPCo_EVP 0
int32_t CP0_MVPConf0;
#define CP0MVPC0_M 31
#define CP0MVPC0_TLBS 29
#define CP0MVPC0_GS 28
#define CP0MVPC0_PCP 27
#define CP0MVPC0_PTLBE 16
#define CP0MVPC0_TCA 15
#define CP0MVPC0_PVPE 10
#define CP0MVPC0_PTC 0
#define CP0MVPC0_M 31
#define CP0MVPC0_TLBS 29
#define CP0MVPC0_GS 28
#define CP0MVPC0_PCP 27
#define CP0MVPC0_PTLBE 16
#define CP0MVPC0_TCA 15
#define CP0MVPC0_PVPE 10
#define CP0MVPC0_PTC 0
int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM 31
#define CP0MVPC1_CIF 30
#define CP0MVPC1_PCX 20
#define CP0MVPC1_PCP2 10
#define CP0MVPC1_PCP1 0
#define CP0MVPC1_CIM 31
#define CP0MVPC1_CIF 30
#define CP0MVPC1_PCX 20
#define CP0MVPC1_PCP2 10
#define CP0MVPC1_PCP1 0
};
typedef struct mips_def_t mips_def_t;
@ -481,44 +494,44 @@ struct CPUMIPSState {
*/
int32_t CP0_Random;
int32_t CP0_VPEControl;
#define CP0VPECo_YSI 21
#define CP0VPECo_GSI 20
#define CP0VPECo_EXCPT 16
#define CP0VPECo_TE 15
#define CP0VPECo_TargTC 0
#define CP0VPECo_YSI 21
#define CP0VPECo_GSI 20
#define CP0VPECo_EXCPT 16
#define CP0VPECo_TE 15
#define CP0VPECo_TargTC 0
int32_t CP0_VPEConf0;
#define CP0VPEC0_M 31
#define CP0VPEC0_XTC 21
#define CP0VPEC0_TCS 19
#define CP0VPEC0_SCS 18
#define CP0VPEC0_DSC 17
#define CP0VPEC0_ICS 16
#define CP0VPEC0_MVP 1
#define CP0VPEC0_VPA 0
#define CP0VPEC0_M 31
#define CP0VPEC0_XTC 21
#define CP0VPEC0_TCS 19
#define CP0VPEC0_SCS 18
#define CP0VPEC0_DSC 17
#define CP0VPEC0_ICS 16
#define CP0VPEC0_MVP 1
#define CP0VPEC0_VPA 0
int32_t CP0_VPEConf1;
#define CP0VPEC1_NCX 20
#define CP0VPEC1_NCP2 10
#define CP0VPEC1_NCP1 0
#define CP0VPEC1_NCX 20
#define CP0VPEC1_NCP2 10
#define CP0VPEC1_NCP1 0
target_ulong CP0_YQMask;
target_ulong CP0_VPESchedule;
target_ulong CP0_VPEScheFBack;
int32_t CP0_VPEOpt;
#define CP0VPEOpt_IWX7 15
#define CP0VPEOpt_IWX6 14
#define CP0VPEOpt_IWX5 13
#define CP0VPEOpt_IWX4 12
#define CP0VPEOpt_IWX3 11
#define CP0VPEOpt_IWX2 10
#define CP0VPEOpt_IWX1 9
#define CP0VPEOpt_IWX0 8
#define CP0VPEOpt_DWX7 7
#define CP0VPEOpt_DWX6 6
#define CP0VPEOpt_DWX5 5
#define CP0VPEOpt_DWX4 4
#define CP0VPEOpt_DWX3 3
#define CP0VPEOpt_DWX2 2
#define CP0VPEOpt_DWX1 1
#define CP0VPEOpt_DWX0 0
#define CP0VPEOpt_IWX7 15
#define CP0VPEOpt_IWX6 14
#define CP0VPEOpt_IWX5 13
#define CP0VPEOpt_IWX4 12
#define CP0VPEOpt_IWX3 11
#define CP0VPEOpt_IWX2 10
#define CP0VPEOpt_IWX1 9
#define CP0VPEOpt_IWX0 8
#define CP0VPEOpt_DWX7 7
#define CP0VPEOpt_DWX6 6
#define CP0VPEOpt_DWX5 5
#define CP0VPEOpt_DWX4 4
#define CP0VPEOpt_DWX3 3
#define CP0VPEOpt_DWX2 2
#define CP0VPEOpt_DWX1 1
#define CP0VPEOpt_DWX0 0
/*
* CP0 Register 2
*/
@ -625,33 +638,33 @@ struct CPUMIPSState {
#define CP0PC_PSN 0 /* 5..0 */
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
#define CP0SRSC0_M 31
#define CP0SRSC0_SRS3 20
#define CP0SRSC0_SRS2 10
#define CP0SRSC0_SRS1 0
#define CP0SRSC0_M 31
#define CP0SRSC0_SRS3 20
#define CP0SRSC0_SRS2 10
#define CP0SRSC0_SRS1 0
int32_t CP0_SRSConf1_rw_bitmask;
int32_t CP0_SRSConf1;
#define CP0SRSC1_M 31
#define CP0SRSC1_SRS6 20
#define CP0SRSC1_SRS5 10
#define CP0SRSC1_SRS4 0
#define CP0SRSC1_M 31
#define CP0SRSC1_SRS6 20
#define CP0SRSC1_SRS5 10
#define CP0SRSC1_SRS4 0
int32_t CP0_SRSConf2_rw_bitmask;
int32_t CP0_SRSConf2;
#define CP0SRSC2_M 31
#define CP0SRSC2_SRS9 20
#define CP0SRSC2_SRS8 10
#define CP0SRSC2_SRS7 0
#define CP0SRSC2_M 31
#define CP0SRSC2_SRS9 20
#define CP0SRSC2_SRS8 10
#define CP0SRSC2_SRS7 0
int32_t CP0_SRSConf3_rw_bitmask;
int32_t CP0_SRSConf3;
#define CP0SRSC3_M 31
#define CP0SRSC3_SRS12 20
#define CP0SRSC3_SRS11 10
#define CP0SRSC3_SRS10 0
#define CP0SRSC3_M 31
#define CP0SRSC3_SRS12 20
#define CP0SRSC3_SRS11 10
#define CP0SRSC3_SRS10 0
int32_t CP0_SRSConf4_rw_bitmask;
int32_t CP0_SRSConf4;
#define CP0SRSC4_SRS15 20
#define CP0SRSC4_SRS14 10
#define CP0SRSC4_SRS13 0
#define CP0SRSC4_SRS15 20
#define CP0SRSC4_SRS14 10
#define CP0SRSC4_SRS13 0
/*
* CP0 Register 7
*/
@ -1090,7 +1103,7 @@ static inline int hflags_mmu_index(uint32_t hflags)
}
}
static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
{
return hflags_mmu_index(env->hflags);
}
@ -1182,7 +1195,7 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
void itc_reconfigure(struct MIPSITUState *tag);
/* helper.c */
target_ulong exception_resume_pc (CPUMIPSState *env);
target_ulong exception_resume_pc(CPUMIPSState *env);
static inline void restore_snan_bit_mode(CPUMIPSState *env)
{