target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
Add emulation of various nanoMIPS load and store instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim
Aleksandar Markovic
parent
821f2008c3
commit
8f1d9b6d63
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@ -17905,10 +17905,287 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_P_GP_BH:
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{
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uint32_t u = extract32(ctx->opcode, 0, 18);
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switch (extract32(ctx->opcode, 18, 3)) {
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case NM_LBGP:
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gen_ld(ctx, OPC_LB, rt, 28, u);
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break;
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case NM_SBGP:
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gen_st(ctx, OPC_SB, rt, 28, u);
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break;
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case NM_LBUGP:
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gen_ld(ctx, OPC_LBU, rt, 28, u);
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break;
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case NM_ADDIUGP_B:
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if (rt != 0) {
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gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], u);
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}
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break;
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case NM_P_GP_LH:
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u &= ~1;
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switch (ctx->opcode & 1) {
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case NM_LHGP:
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gen_ld(ctx, OPC_LH, rt, 28, u);
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break;
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case NM_LHUGP:
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gen_ld(ctx, OPC_LHU, rt, 28, u);
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break;
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}
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break;
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case NM_P_GP_SH:
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u &= ~1;
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switch (ctx->opcode & 1) {
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case NM_SHGP:
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gen_st(ctx, OPC_SH, rt, 28, u);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_GP_CP1:
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u &= ~0x3;
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switch (ctx->opcode & 0x3) {
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case NM_LWC1GP:
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gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
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break;
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case NM_LDC1GP:
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gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
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break;
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case NM_SWC1GP:
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gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
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break;
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case NM_SDC1GP:
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gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
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break;
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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}
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break;
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case NM_P_LS_U12:
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{
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uint32_t u = extract32(ctx->opcode, 0, 12);
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switch (extract32(ctx->opcode, 12, 4)) {
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case NM_P_PREFU12:
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if (rt == 31) {
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/* SYNCI */
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/* Break the TB to be able to sync copied instructions
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immediately */
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ctx->base.is_jmp = DISAS_STOP;
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} else {
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/* PREF */
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/* Treat as NOP. */
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}
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break;
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case NM_LB:
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gen_ld(ctx, OPC_LB, rt, rs, u);
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break;
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case NM_LH:
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gen_ld(ctx, OPC_LH, rt, rs, u);
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break;
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case NM_LW:
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gen_ld(ctx, OPC_LW, rt, rs, u);
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break;
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case NM_LBU:
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gen_ld(ctx, OPC_LBU, rt, rs, u);
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break;
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case NM_LHU:
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gen_ld(ctx, OPC_LHU, rt, rs, u);
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break;
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case NM_SB:
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gen_st(ctx, OPC_SB, rt, rs, u);
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break;
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case NM_SH:
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gen_st(ctx, OPC_SH, rt, rs, u);
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break;
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case NM_SW:
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gen_st(ctx, OPC_SW, rt, rs, u);
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break;
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case NM_LWC1:
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gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
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break;
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case NM_LDC1:
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gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
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break;
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case NM_SWC1:
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gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
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break;
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case NM_SDC1:
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gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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}
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break;
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case NM_P_LS_S9:
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{
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int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
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extract32(ctx->opcode, 0, 8);
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switch (extract32(ctx->opcode, 8, 3)) {
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case NM_P_LS_S0:
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switch (extract32(ctx->opcode, 11, 4)) {
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case NM_LBS9:
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gen_ld(ctx, OPC_LB, rt, rs, s);
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break;
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case NM_LHS9:
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gen_ld(ctx, OPC_LH, rt, rs, s);
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break;
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case NM_LWS9:
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gen_ld(ctx, OPC_LW, rt, rs, s);
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break;
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case NM_LBUS9:
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gen_ld(ctx, OPC_LBU, rt, rs, s);
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break;
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case NM_LHUS9:
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gen_ld(ctx, OPC_LHU, rt, rs, s);
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break;
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case NM_SBS9:
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gen_st(ctx, OPC_SB, rt, rs, s);
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break;
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case NM_SHS9:
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gen_st(ctx, OPC_SH, rt, rs, s);
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break;
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case NM_SWS9:
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gen_st(ctx, OPC_SW, rt, rs, s);
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break;
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case NM_LWC1S9:
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gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);
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break;
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case NM_LDC1S9:
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gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);
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break;
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case NM_SWC1S9:
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gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);
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break;
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case NM_SDC1S9:
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gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);
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break;
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case NM_P_PREFS9:
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if (rt == 31) {
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/* SYNCI */
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/* Break the TB to be able to sync copied instructions
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immediately */
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ctx->base.is_jmp = DISAS_STOP;
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} else {
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/* PREF */
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/* Treat as NOP. */
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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break;
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case NM_P_LS_S1:
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switch (extract32(ctx->opcode, 11, 4)) {
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case NM_UALH:
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case NM_UASH:
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, rs, s);
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switch (extract32(ctx->opcode, 11, 4)) {
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case NM_UALH:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
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MO_UNALN);
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gen_store_gpr(t0, rt);
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break;
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case NM_UASH:
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gen_load_gpr(t1, rt);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
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MO_UNALN);
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break;
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}
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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break;
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case NM_P_LL:
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switch (ctx->opcode & 0x03) {
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case NM_LL:
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gen_ld(ctx, OPC_LL, rt, rs, s);
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break;
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case NM_LLWP:
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break;
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}
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break;
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case NM_P_SC:
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switch (ctx->opcode & 0x03) {
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case NM_SC:
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gen_st_cond(ctx, OPC_SC, rt, rs, s);
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break;
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case NM_SCWP:
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break;
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}
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break;
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case NM_CACHE:
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check_cp0_enabled(ctx);
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if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
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gen_cache_operation(ctx, rt, rs, s);
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}
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break;
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}
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break;
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case NM_P_LS_WM:
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case NM_P_LS_UAWM:
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{
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int count = extract32(ctx->opcode, 12, 3);
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int counter = 0;
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offset = sextract32(ctx->opcode, 15, 1) << 8 |
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extract32(ctx->opcode, 0, 8);
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TCGv va = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGMemOp memop = (extract32(ctx->opcode, 8, 3)) ==
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NM_P_LS_UAWM ? MO_UNALN : 0;
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count = (count == 0) ? 8 : count;
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while (counter != count) {
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int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);
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int this_offset = offset + (counter << 2);
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gen_base_offset_addr(ctx, va, rs, this_offset);
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switch (extract32(ctx->opcode, 11, 1)) {
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case NM_LWM:
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tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
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memop | MO_TESL);
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gen_store_gpr(t1, this_rt);
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if ((this_rt == rs) &&
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(counter != (count - 1))) {
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/* UNPREDICTABLE */
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}
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break;
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case NM_SWM:
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this_rt = (rt == 0) ? 0 : this_rt;
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gen_load_gpr(t1, this_rt);
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tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
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memop | MO_TEUL);
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break;
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}
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counter++;
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}
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tcg_temp_free(va);
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tcg_temp_free(t1);
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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}
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break;
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case NM_MOVE_BALC:
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break;
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