cpu_ldst.h: Allow NB_MMU_MODES to be 7
Support guest CPUs which need 7 MMU index values. Add a comment about what would be required to raise the limit further (trivial for 8, TCG backend rework for 9 or more). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -244,9 +244,31 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 6) */
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#if (NB_MMU_MODES > 6)
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#error "NB_MMU_MODES > 6 is not supported for now"
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#endif /* (NB_MMU_MODES > 6) */
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#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
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#define CPU_MMU_INDEX 6
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#define MEMSUFFIX MMU_MODE6_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 7) */
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#if (NB_MMU_MODES > 7)
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/* Note that supporting NB_MMU_MODES == 9 would require
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* changes to at least the ARM TCG backend.
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*/
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#error "NB_MMU_MODES > 7 is not supported for now"
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#endif /* (NB_MMU_MODES > 7) */
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/* these access are slower, they must be as rare as possible */
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#define CPU_MMU_INDEX (cpu_mmu_index(env))
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