target-i386: fix over 80 chars warnings
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
liguang
Blue Swirl
parent
0bc60a8ae0
commit
90a2541b76
@ -122,7 +122,8 @@ void helper_cpuid(CPUX86State *env)
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cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
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cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx);
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cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
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&eax, &ebx, &ecx, &edx);
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env->regs[R_EAX] = eax;
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env->regs[R_EBX] = ebx;
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env->regs[R_ECX] = ecx;
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@ -271,7 +272,8 @@ void helper_wrmsr(CPUX86State *env)
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
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val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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val = ((uint32_t)env->regs[R_EAX]) |
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((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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switch ((uint32_t)env->regs[R_ECX]) {
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case MSR_IA32_SYSENTER_CS:
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@ -350,7 +352,8 @@ void helper_wrmsr(CPUX86State *env)
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val;
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base = val;
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break;
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case MSR_MTRRphysMask(0):
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case MSR_MTRRphysMask(1):
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@ -360,14 +363,17 @@ void helper_wrmsr(CPUX86State *env)
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case MSR_MTRRphysMask(5):
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case MSR_MTRRphysMask(6):
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case MSR_MTRRphysMask(7):
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env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val;
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env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysMask(0)) / 2].mask = val;
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break;
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case MSR_MTRRfix64K_00000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val;
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix64K_00000] = val;
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break;
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case MSR_MTRRfix16K_80000:
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case MSR_MTRRfix16K_A0000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val;
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix16K_80000 + 1] = val;
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break;
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case MSR_MTRRfix4K_C0000:
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case MSR_MTRRfix4K_C8000:
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@ -377,7 +383,8 @@ void helper_wrmsr(CPUX86State *env)
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case MSR_MTRRfix4K_E8000:
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case MSR_MTRRfix4K_F0000:
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case MSR_MTRRfix4K_F8000:
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val;
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env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix4K_C0000 + 3] = val;
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break;
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case MSR_MTRRdefType:
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env->mtrr_deftype = val;
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@ -399,7 +406,8 @@ void helper_wrmsr(CPUX86State *env)
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break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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(4 * env->mcg_cap & 0xff)) {
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uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
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if ((offset & 0x3) != 0
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|| (val == 0 || val == ~(uint64_t)0)) {
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@ -480,7 +488,8 @@ void helper_rdmsr(CPUX86State *env)
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case MSR_MTRRphysBase(5):
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case MSR_MTRRphysBase(6):
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case MSR_MTRRphysBase(7):
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base;
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysBase(0)) / 2].base;
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break;
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case MSR_MTRRphysMask(0):
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case MSR_MTRRphysMask(1):
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@ -490,14 +499,16 @@ void helper_rdmsr(CPUX86State *env)
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case MSR_MTRRphysMask(5):
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case MSR_MTRRphysMask(6):
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case MSR_MTRRphysMask(7):
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask;
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val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
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MSR_MTRRphysMask(0)) / 2].mask;
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break;
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case MSR_MTRRfix64K_00000:
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val = env->mtrr_fixed[0];
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break;
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case MSR_MTRRfix16K_80000:
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case MSR_MTRRfix16K_A0000:
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1];
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix16K_80000 + 1];
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break;
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case MSR_MTRRfix4K_C0000:
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case MSR_MTRRfix4K_C8000:
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@ -507,7 +518,8 @@ void helper_rdmsr(CPUX86State *env)
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case MSR_MTRRfix4K_E8000:
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case MSR_MTRRfix4K_F0000:
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case MSR_MTRRfix4K_F8000:
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3];
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val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
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MSR_MTRRfix4K_C0000 + 3];
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break;
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case MSR_MTRRdefType:
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val = env->mtrr_deftype;
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@ -539,7 +551,8 @@ void helper_rdmsr(CPUX86State *env)
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break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) {
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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(4 * env->mcg_cap & 0xff)) {
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uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
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val = env->mce_banks[offset];
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break;
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@ -1811,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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if (!(e2 & DESC_C_MASK) && dpl < cpl) {
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/* to inner privilege */
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get_ss_esp_from_tss(env, &ss, &sp, dpl);
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LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx
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"\n",
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ss, sp, param_count, env->regs[R_ESP]);
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LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
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TARGET_FMT_lx "\n", ss, sp, param_count,
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env->regs[R_ESP]);
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if ((ss & 0xfffc) == 0) {
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raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
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}
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@ -1847,16 +1847,18 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
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PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
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for (i = param_count - 1; i >= 0; i--) {
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val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) &
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old_sp_mask));
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val = cpu_ldl_kernel(env, old_ssp +
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((env->regs[R_ESP] + i * 4) &
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old_sp_mask));
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PUSHL(ssp, sp, sp_mask, val);
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}
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} else {
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PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
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PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
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for (i = param_count - 1; i >= 0; i--) {
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val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) &
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old_sp_mask));
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val = cpu_lduw_kernel(env, old_ssp +
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((env->regs[R_ESP] + i * 2) &
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old_sp_mask));
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PUSHW(ssp, sp, sp_mask, val);
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}
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}
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@ -658,8 +658,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
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R_DS);
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env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
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env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp));
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env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax));
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env->regs[R_ESP] = ldq_phys(env->vm_hsave +
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offsetof(struct vmcb, save.rsp));
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env->regs[R_EAX] = ldq_phys(env->vm_hsave +
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offsetof(struct vmcb, save.rax));
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env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
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env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));
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