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target-i386: fix over 80 chars warnings

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Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson  <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
liguang 2013-05-28 16:21:10 +08:00 committed by Blue Swirl
parent 0bc60a8ae0
commit 90a2541b76
3 changed files with 39 additions and 22 deletions
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39
target-i386/misc_helper.c
View File

@ -122,7 +122,8 @@ void helper_cpuid(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0); cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx); cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
&eax, &ebx, &ecx, &edx);
env->regs[R_EAX] = eax; env->regs[R_EAX] = eax;
env->regs[R_EBX] = ebx; env->regs[R_EBX] = ebx;
env->regs[R_ECX] = ecx; env->regs[R_ECX] = ecx;
@ -271,7 +272,8 @@ void helper_wrmsr(CPUX86State *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1); cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); val = ((uint32_t)env->regs[R_EAX]) |
((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
switch ((uint32_t)env->regs[R_ECX]) { switch ((uint32_t)env->regs[R_ECX]) {
case MSR_IA32_SYSENTER_CS: case MSR_IA32_SYSENTER_CS:
@ -350,7 +352,8 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7): case MSR_MTRRphysBase(7):
env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val; env->mtrr_var[((uint32_t)env->regs[R_ECX] -
MSR_MTRRphysBase(0)) / 2].base = val;
break; break;
case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1): case MSR_MTRRphysMask(1):
@ -360,14 +363,17 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7): case MSR_MTRRphysMask(7):
env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val; env->mtrr_var[((uint32_t)env->regs[R_ECX] -
MSR_MTRRphysMask(0)) / 2].mask = val;
break; break;
case MSR_MTRRfix64K_00000: case MSR_MTRRfix64K_00000:
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val; env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
MSR_MTRRfix64K_00000] = val;
break; break;
case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000: case MSR_MTRRfix16K_A0000:
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val; env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
MSR_MTRRfix16K_80000 + 1] = val;
break; break;
case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000: case MSR_MTRRfix4K_C8000:
@ -377,7 +383,8 @@ void helper_wrmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000: case MSR_MTRRfix4K_F8000:
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val; env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
MSR_MTRRfix4K_C0000 + 3] = val;
break; break;
case MSR_MTRRdefType: case MSR_MTRRdefType:
env->mtrr_deftype = val; env->mtrr_deftype = val;
@ -399,7 +406,8 @@ void helper_wrmsr(CPUX86State *env)
break; break;
default: default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
(4 * env->mcg_cap & 0xff)) {
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
if ((offset & 0x3) != 0 if ((offset & 0x3) != 0
|| (val == 0 || val == ~(uint64_t)0)) { || (val == 0 || val == ~(uint64_t)0)) {
@ -480,7 +488,8 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7): case MSR_MTRRphysBase(7):
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base; val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
MSR_MTRRphysBase(0)) / 2].base;
break; break;
case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1): case MSR_MTRRphysMask(1):
@ -490,14 +499,16 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7): case MSR_MTRRphysMask(7):
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask; val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
MSR_MTRRphysMask(0)) / 2].mask;
break; break;
case MSR_MTRRfix64K_00000: case MSR_MTRRfix64K_00000:
val = env->mtrr_fixed[0]; val = env->mtrr_fixed[0];
break; break;
case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000: case MSR_MTRRfix16K_A0000:
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1]; val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
MSR_MTRRfix16K_80000 + 1];
break; break;
case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000: case MSR_MTRRfix4K_C8000:
@ -507,7 +518,8 @@ void helper_rdmsr(CPUX86State *env)
case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000: case MSR_MTRRfix4K_F8000:
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3]; val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
MSR_MTRRfix4K_C0000 + 3];
break; break;
case MSR_MTRRdefType: case MSR_MTRRdefType:
val = env->mtrr_deftype; val = env->mtrr_deftype;
@ -539,7 +551,8 @@ void helper_rdmsr(CPUX86State *env)
break; break;
default: default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
(4 * env->mcg_cap & 0xff)) {
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
val = env->mce_banks[offset]; val = env->mce_banks[offset];
break; break;

12
target-i386/seg_helper.c
View File

@ -1811,9 +1811,9 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) { if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */ /* to inner privilege */
get_ss_esp_from_tss(env, &ss, &sp, dpl); get_ss_esp_from_tss(env, &ss, &sp, dpl);
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]=" TARGET_FMT_lx LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
"\n", TARGET_FMT_lx "\n", ss, sp, param_count,
ss, sp, param_count, env->regs[R_ESP]); env->regs[R_ESP]);
if ((ss & 0xfffc) == 0) { if ((ss & 0xfffc) == 0) {
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc); raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
} }
@ -1847,7 +1847,8 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]); PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) { for (i = param_count - 1; i >= 0; i--) {
val = cpu_ldl_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 4) & val = cpu_ldl_kernel(env, old_ssp +
((env->regs[R_ESP] + i * 4) &
old_sp_mask)); old_sp_mask));
PUSHL(ssp, sp, sp_mask, val); PUSHL(ssp, sp, sp_mask, val);
} }
@ -1855,7 +1856,8 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]); PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) { for (i = param_count - 1; i >= 0; i--) {
val = cpu_lduw_kernel(env, old_ssp + ((env->regs[R_ESP] + i * 2) & val = cpu_lduw_kernel(env, old_ssp +
((env->regs[R_ESP] + i * 2) &
old_sp_mask)); old_sp_mask));
PUSHW(ssp, sp, sp_mask, val); PUSHW(ssp, sp, sp_mask, val);
} }

6
target-i386/svm_helper.c
View File

@ -658,8 +658,10 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
R_DS); R_DS);
env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip)); env->eip = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rip));
env->regs[R_ESP] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rsp)); env->regs[R_ESP] = ldq_phys(env->vm_hsave +
env->regs[R_EAX] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.rax)); offsetof(struct vmcb, save.rsp));
env->regs[R_EAX] = ldq_phys(env->vm_hsave +
offsetof(struct vmcb, save.rax));
env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6)); env->dr[6] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr6));
env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7)); env->dr[7] = ldq_phys(env->vm_hsave + offsetof(struct vmcb, save.dr7));