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target/arm: Make RVBAR available for all ARMv8 CPUs 

RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tobias Röhmel 2022-12-06 11:24:59 +01:00 committed by Peter Maydell
parent c7f786abe2
commit 910e4f2497
2 changed files with 19 additions and 8 deletions
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6
target/arm/cpu.c
View File

@ -309,6 +309,10 @@ static void arm_cpu_reset_hold(Object *obj)
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
CPACR, CP11, 3); CPACR, CP11, 3);
#endif #endif
if (arm_feature(env, ARM_FEATURE_V8)) {
env->cp15.rvbar = cpu->rvbar_prop;
env->regs[15] = cpu->rvbar_prop;
}
} }
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -1345,7 +1349,7 @@ void arm_cpu_post_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
} }
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
object_property_add_uint64_ptr(obj, "rvbar", object_property_add_uint64_ptr(obj, "rvbar",
&cpu->rvbar_prop, &cpu->rvbar_prop,
OBJ_PROP_FLAG_READWRITE); OBJ_PROP_FLAG_READWRITE);

13
target/arm/helper.c
View File

@ -7896,7 +7896,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (!arm_feature(env, ARM_FEATURE_EL3) && if (!arm_feature(env, ARM_FEATURE_EL3) &&
!arm_feature(env, ARM_FEATURE_EL2)) { !arm_feature(env, ARM_FEATURE_EL2)) {
ARMCPRegInfo rvbar = { ARMCPRegInfo rvbar = {
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL1_R, .access = PL1_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
@ -7987,13 +7987,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} }
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */ /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
if (!arm_feature(env, ARM_FEATURE_EL3)) { if (!arm_feature(env, ARM_FEATURE_EL3)) {
ARMCPRegInfo rvbar = { ARMCPRegInfo rvbar[] = {
{
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL2_R, .access = PL2_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar), .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
},
{ .name = "RVBAR", .type = ARM_CP_ALIAS,
.cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
.access = PL2_R,
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
},
}; };
define_one_arm_cp_reg(cpu, &rvbar); define_arm_cp_regs(cpu, rvbar);
} }
} }