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s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC) 

Just like BRANCH ON CONDITION - however the address is read from memory
(always 8 bytes are read), we have to wrap the address manually. The
address is read using current CPU DAT/address-space controls, just like
ordinary data.

Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200928122717.30586-7-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
David Hildenbrand 2020-09-28 14:27:14 +02:00 committed by Cornelia Huck
parent 6645e4542f
commit 9131bd01ec
2 changed files with 10 additions and 0 deletions
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2
target/s390x/insn-data.def
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@ -115,6 +115,8 @@
/* BRANCH RELATIVE AND SAVE */
C(0xa705, BRAS, RI_b, Z, 0, 0, r1, 0, basi, 0)
C(0xc005, BRASL, RIL_b, Z, 0, 0, r1, 0, basi, 0)
/* BRANCH INDIRECT ON CONDITION */
C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0)
/* BRANCH ON CONDITION */
C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0)
C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0)

8
target/s390x/translate.c
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@ -5956,6 +5956,14 @@ static void in2_m2_64(DisasContext *s, DisasOps *o)
}
#define SPEC_in2_m2_64 0
static void in2_m2_64w(DisasContext *s, DisasOps *o)
{
in2_a2(s, o);
tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
}
#define SPEC_in2_m2_64w 0
#ifndef CONFIG_USER_ONLY
static void in2_m2_64a(DisasContext *s, DisasOps *o)
{