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Push common interrupt variables to cpu-defs.h (Glauber Costa) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2008-05-29 10:08:06 +00:00
parent 4369415f1e
commit 9133e39b84
10 changed files with 4 additions and 18 deletions
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4
cpu-defs.h
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@ -160,6 +160,10 @@ typedef struct CPUTLBEntry {
int nb_watchpoints; \
int watchpoint_hit; \
\
/* Core interrupt code */ \
jmp_buf jmp_env; \
int exception_index; \
\
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
/* user data */ \

2
target-alpha/cpu.h
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@ -282,11 +282,9 @@ struct CPUAlphaState {
/* Those resources are used only in Qemu core */
CPU_COMMON
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
uint32_t hflags;
int exception_index;
int error_code;
int interrupt_request;

2
target-arm/cpu.h
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@ -157,8 +157,6 @@ typedef struct CPUARMState {
void *irq_opaque;
/* exception/interrupt handling */
jmp_buf jmp_env;
int exception_index;
int interrupt_request;
int user_mode_only;

2
target-cris/cpu.h
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@ -123,7 +123,6 @@ typedef struct CPUCRISState {
/* X flag at the time of cc snapshot. */
int cc_x;
int exception_index;
int interrupt_request;
int interrupt_vector;
int fault_vector;
@ -158,7 +157,6 @@ typedef struct CPUCRISState {
int features;
int user_mode_only;
jmp_buf jmp_env;
CPU_COMMON
} CPUCRISState;

2
target-i386/cpu.h
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@ -552,8 +552,6 @@ typedef struct CPUX86State {
uint64_t pat;
/* exception/interrupt handling */
jmp_buf jmp_env;
int exception_index;
int error_code;
int exception_is_int;
target_ulong exception_next_eip;

2
target-m68k/cpu.h
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@ -104,8 +104,6 @@ typedef struct CPUM68KState {
uint32_t t1;
/* exception/interrupt handling */
jmp_buf jmp_env;
int exception_index;
int interrupt_request;
int user_mode_only;

2
target-mips/cpu.h
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@ -412,8 +412,6 @@ struct CPUMIPSState {
int32_t CP0_DESAVE;
/* Qemu */
int interrupt_request;
jmp_buf jmp_env;
int exception_index;
int error_code;
int user_mode_only; /* user mode only simulation */
uint32_t hflags; /* CPU State */

2
target-ppc/cpu.h
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@ -646,7 +646,6 @@ struct CPUPPCState {
int bfd_mach;
uint32_t flags;
int exception_index;
int error_code;
int interrupt_request;
uint32_t pending_interrupts;
@ -672,7 +671,6 @@ struct CPUPPCState {
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */

2
target-sh4/cpu.h
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@ -114,10 +114,8 @@ typedef struct CPUSH4State {
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
jmp_buf jmp_env;
int user_mode_only;
int interrupt_request;
int exception_index;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;

2
target-sparc/cpu.h
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@ -214,9 +214,7 @@ typedef struct CPUSPARCState {
uint32_t pil_in; /* incoming interrupt level bitmap */
int psref; /* enable fpu */
target_ulong version;
jmp_buf jmp_env;
int user_mode_only;
int exception_index;
int interrupt_index;
int interrupt_request;
uint32_t mmu_bm;