target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:53 +05:30 committed by Alistair Francis
parent d207863cd3
commit 91870b510a
2 changed files with 6 additions and 0 deletions

View File

@ -537,6 +537,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
}
if (cpu->cfg.aia) {
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@ -782,6 +786,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),

View File

@ -376,6 +376,7 @@ struct RISCVCPUConfig {
bool mmu;
bool pmp;
bool epmp;
bool aia;
uint64_t resetvec;
};