target/riscv: Allow users to force enable AIA CSRs in HART
We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-18-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -537,6 +537,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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}
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if (cpu->cfg.aia) {
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riscv_set_feature(env, RISCV_FEATURE_AIA);
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}
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set_resetvec(env, cpu->cfg.resetvec);
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/* Validate that MISA_MXL is set properly. */
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@ -782,6 +786,7 @@ static Property riscv_cpu_properties[] = {
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DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
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/* ePMP 0.9.3 */
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DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
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DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
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DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
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DEFINE_PROP_END_OF_LIST(),
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@ -376,6 +376,7 @@ struct RISCVCPUConfig {
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bool mmu;
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bool pmp;
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bool epmp;
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bool aia;
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uint64_t resetvec;
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};
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