ppc/pnv: add PHB3 bus init helper
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio regions, registering it via pci_register_root_bus() and then setup the iommu. We'll want to init the bus from outside pnv_phb3.c when the bus is removed from the PnvPHB3 device and put into a new parent PnvPHB device. The new pnv_phb3_bus_init() helper will be used by the parent to init the bus when using the PHB3 backend. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20220624084921.399219-2-danielhb413@gmail.com>
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@ -986,6 +986,28 @@ static void pnv_phb3_instance_init(Object *obj)
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}
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}
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void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb)
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{
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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/*
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* PHB3 doesn't support IO space. However, qemu gets very upset if
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* we don't have an IO region to anchor IO BARs onto so we just
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* initialize one which we never hook up to anything
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*/
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memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
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memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
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PCI_MMIO_TOTAL_SIZE);
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pci->bus = pci_register_root_bus(dev,
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dev->id ? dev->id : NULL,
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pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
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&phb->pci_mmio, &phb->pci_io,
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0, 4, TYPE_PNV_PHB3_ROOT_BUS);
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pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
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}
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static void pnv_phb3_realize(DeviceState *dev, Error **errp)
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static void pnv_phb3_realize(DeviceState *dev, Error **errp)
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{
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{
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PnvPHB3 *phb = PNV_PHB3(dev);
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PnvPHB3 *phb = PNV_PHB3(dev);
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@ -1035,22 +1057,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
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memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
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memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb3_reg_ops, phb,
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"phb3-regs", 0x1000);
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"phb3-regs", 0x1000);
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/*
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pnv_phb3_bus_init(dev, phb);
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* PHB3 doesn't support IO space. However, qemu gets very upset if
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* we don't have an IO region to anchor IO BARs onto so we just
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* initialize one which we never hook up to anything
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*/
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memory_region_init(&phb->pci_io, OBJECT(phb), "pci-io", 0x10000);
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memory_region_init(&phb->pci_mmio, OBJECT(phb), "pci-mmio",
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PCI_MMIO_TOTAL_SIZE);
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pci->bus = pci_register_root_bus(dev,
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dev->id ? dev->id : NULL,
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pnv_phb3_set_irq, pnv_phb3_map_irq, phb,
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&phb->pci_mmio, &phb->pci_io,
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0, 4, TYPE_PNV_PHB3_ROOT_BUS);
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pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
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pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
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pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
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phb->phb_id, phb->chip_id);
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phb->phb_id, phb->chip_id);
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@ -164,5 +164,6 @@ uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
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void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
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void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
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void pnv_phb3_update_regions(PnvPHB3 *phb);
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void pnv_phb3_update_regions(PnvPHB3 *phb);
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void pnv_phb3_remap_irqs(PnvPHB3 *phb);
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void pnv_phb3_remap_irqs(PnvPHB3 *phb);
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void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
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#endif /* PCI_HOST_PNV_PHB3_H */
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#endif /* PCI_HOST_PNV_PHB3_H */
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