disable PCI device for PMAC
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@966 c046a42c-6fe2-441c-8c8c-71466251a162
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e2733d20b2
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55
hw/openpic.c
55
hw/openpic.c
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@ -164,6 +164,7 @@ typedef struct IRQ_dst_t {
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struct openpic_t {
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struct openpic_t {
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PCIDevice pci_dev;
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PCIDevice pci_dev;
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int mem_index;
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/* Global registers */
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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uint32_t frep; /* Feature reporting register */
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uint32_t glbc; /* Global configuration register */
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uint32_t glbc; /* Global configuration register */
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@ -937,7 +938,6 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type)
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uint32_t addr, uint32_t size, int type)
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{
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{
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openpic_t *opp;
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openpic_t *opp;
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int opp_io_memory;
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DPRINTF("Map OpenPIC\n");
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DPRINTF("Map OpenPIC\n");
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opp = (openpic_t *)pci_dev;
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opp = (openpic_t *)pci_dev;
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@ -953,9 +953,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
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/* Per CPU registers */
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/* Per CPU registers */
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DPRINTF("Register OPENPIC dst %08x => %08x\n",
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DPRINTF("Register OPENPIC dst %08x => %08x\n",
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addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
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addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
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opp_io_memory = cpu_register_io_memory(0, openpic_read,
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cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
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openpic_write, opp);
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cpu_register_physical_memory(addr, 0x40000, opp_io_memory);
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#if 0 // Don't implement ISU for now
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#if 0 // Don't implement ISU for now
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opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
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opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
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openpic_src_write);
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openpic_src_write);
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@ -964,8 +962,7 @@ static void openpic_map(PCIDevice *pci_dev, int region_num,
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#endif
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#endif
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}
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}
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openpic_t *openpic_init (PCIBus *bus,
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openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus)
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uint32_t isu_base, uint32_t idu_base, int nb_cpus)
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{
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{
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openpic_t *opp;
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openpic_t *opp;
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uint8_t *pci_conf;
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uint8_t *pci_conf;
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@ -974,25 +971,32 @@ openpic_t *openpic_init (PCIBus *bus,
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/* XXX: for now, only one CPU is supported */
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/* XXX: for now, only one CPU is supported */
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if (nb_cpus != 1)
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if (nb_cpus != 1)
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return NULL;
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return NULL;
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opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
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if (bus) {
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-1, NULL, NULL);
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opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
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if (opp == NULL)
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-1, NULL, NULL);
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return NULL;
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if (opp == NULL)
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pci_conf = opp->pci_dev.config;
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return NULL;
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pci_conf[0x00] = 0x14; // IBM MPIC2
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pci_conf = opp->pci_dev.config;
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pci_conf[0x01] = 0x10;
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pci_conf[0x00] = 0x14; // IBM MPIC2
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pci_conf[0x02] = 0xFF;
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pci_conf[0x01] = 0x10;
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pci_conf[0x03] = 0xFF;
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pci_conf[0x02] = 0xFF;
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pci_conf[0x0a] = 0x80; // PIC
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pci_conf[0x03] = 0xFF;
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pci_conf[0x0b] = 0x08;
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pci_conf[0x0a] = 0x80; // PIC
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pci_conf[0x0e] = 0x00; // header_type
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pci_conf[0x0b] = 0x08;
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pci_conf[0x3d] = 0x00; // no interrupt pin
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pci_conf[0x0e] = 0x00; // header_type
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pci_conf[0x3d] = 0x00; // no interrupt pin
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/* Register I/O spaces */
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pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
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PCI_ADDRESS_SPACE_MEM, &openpic_map);
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} else {
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opp = qemu_mallocz(sizeof(openpic_t));
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}
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/* Register I/O spaces */
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opp->mem_index = cpu_register_io_memory(0, openpic_read,
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pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
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openpic_write, opp);
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PCI_ADDRESS_SPACE_MEM, &openpic_map);
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// isu_base &= 0xFFFC0000;
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isu_base &= 0xFFFC0000;
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opp->nb_cpus = nb_cpus;
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opp->nb_cpus = nb_cpus;
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/* Set IRQ types */
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/* Set IRQ types */
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for (i = 0; i < EXT_IRQ; i++) {
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for (i = 0; i < EXT_IRQ; i++) {
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@ -1013,6 +1017,7 @@ openpic_t *openpic_init (PCIBus *bus,
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opp->src[i].type = IRQ_INTERNAL;
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opp->src[i].type = IRQ_INTERNAL;
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}
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}
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openpic_reset(opp);
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openpic_reset(opp);
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if (pmem_index)
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*pmem_index = opp->mem_index;
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return opp;
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return opp;
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}
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}
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@ -36,6 +36,7 @@ static int dbdma_mem_index;
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static int cuda_mem_index;
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static int cuda_mem_index;
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static int ide0_mem_index;
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static int ide0_mem_index;
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static int ide1_mem_index;
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static int ide1_mem_index;
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static int openpic_mem_index;
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/* DBDMA: currently no op - should suffice right now */
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/* DBDMA: currently no op - should suffice right now */
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@ -87,6 +88,7 @@ static void macio_map(PCIDevice *pci_dev, int region_num,
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
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cpu_register_physical_memory(addr + 0x40000, 0x40000, openpic_mem_index);
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}
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}
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static void macio_init(PCIBus *bus)
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static void macio_init(PCIBus *bus)
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@ -191,7 +193,7 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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/* init basic PC hardware */
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/* init basic PC hardware */
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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vga_ram_size);
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openpic = openpic_init(pci_bus, 0x00000000, 0xF0000000, 1);
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openpic = openpic_init(NULL, &openpic_mem_index, 1);
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pci_pmac_set_openpic(pci_bus, openpic);
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pci_pmac_set_openpic(pci_bus, openpic);
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/* XXX: suppress that */
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/* XXX: suppress that */
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