hw/misc: Introduce AMD/Xilix Versal TRNG device
This adds a non-cryptographic grade implementation of the model for the True Random Number Generator (TRNG) component in AMD/Xilinx Versal device family. This implements all 3 modes defined by the actual hardware specs, all of which selectable by guest software at will at anytime: 1) PRNG mode, in which the generated sequence is required to be reproducible after reseeded by the same 384-bit value as supplied by guest software. 2) Test mode, in which the generated sequence is required to be reproducible ater reseeded by the same 128-bit test seed supplied by guest software. 3) TRNG mode, in which non-reproducible sequence is generated based on periodic reseed by a suitable entropy source. This model is only intended for non-real world testing of guest software, where cryptographically strong PRNG or TRNG is not needed. This model supports versions 1 & 2 of the device, with default to be version 2; the 'hw-version' uint32 property can be set to 0x0100 to override the default. Other implemented properties: - 'forced-prng', uint64 When set to non-zero, mode 3's entropy source is implemented as a deterministic sequence based on the given value and other deterministic parameters. This option allows the emulation to test guest software using mode 3 and to reproduce data-dependent defects. - 'fips-fault-events', uint32, bit-mask bit 3: Triggers the SP800-90B entropy health test fault irq bit 1: Triggers the FIPS 140-2 continuous test fault irq Signed-off-by: Tong Ho <tong.ho@amd.com> Message-id: 20231031184611.3029156-2-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tong Ho
Peter Maydell
parent
4c09abeae8
commit
921923583f
@ -197,4 +197,7 @@ config DJMEMC
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config IOSB
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bool
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config XLNX_VERSAL_TRNG
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bool
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source macio/Kconfig
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@ -104,6 +104,9 @@ system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
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'xlnx-cfi-if.c',
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'xlnx-versal-cframe-reg.c',
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))
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system_ss.add(when: 'CONFIG_XLNX_VERSAL_TRNG', if_true: files(
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'xlnx-versal-trng.c',
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))
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system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c'))
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system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
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system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
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717
hw/misc/xlnx-versal-trng.c
Normal file
717
hw/misc/xlnx-versal-trng.c
Normal file
@ -0,0 +1,717 @@
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/*
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* Non-crypto strength model of the True Random Number Generator
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* in the AMD/Xilinx Versal device family.
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*
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* Copyright (c) 2017-2020 Xilinx Inc.
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* Copyright (c) 2023 Advanced Micro Devices, Inc.
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/xlnx-versal-trng.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qemu/guest-random.h"
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#include "qemu/timer.h"
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#include "qapi/visitor.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#ifndef XLNX_VERSAL_TRNG_ERR_DEBUG
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#define XLNX_VERSAL_TRNG_ERR_DEBUG 0
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#endif
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REG32(INT_CTRL, 0x0)
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FIELD(INT_CTRL, CERTF_RST, 5, 1)
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FIELD(INT_CTRL, DTF_RST, 4, 1)
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FIELD(INT_CTRL, DONE_RST, 3, 1)
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FIELD(INT_CTRL, CERTF_EN, 2, 1)
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FIELD(INT_CTRL, DTF_EN, 1, 1)
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FIELD(INT_CTRL, DONE_EN, 0, 1)
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REG32(STATUS, 0x4)
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FIELD(STATUS, QCNT, 9, 3)
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FIELD(STATUS, EAT, 4, 5)
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FIELD(STATUS, CERTF, 3, 1)
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FIELD(STATUS, DTF, 1, 1)
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FIELD(STATUS, DONE, 0, 1)
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REG32(CTRL, 0x8)
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FIELD(CTRL, PERSODISABLE, 10, 1)
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FIELD(CTRL, SINGLEGENMODE, 9, 1)
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FIELD(CTRL, EUMODE, 8, 1)
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FIELD(CTRL, PRNGMODE, 7, 1)
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FIELD(CTRL, TSTMODE, 6, 1)
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FIELD(CTRL, PRNGSTART, 5, 1)
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FIELD(CTRL, EATAU, 4, 1)
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FIELD(CTRL, PRNGXS, 3, 1)
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FIELD(CTRL, TRSSEN, 2, 1)
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FIELD(CTRL, QERTUEN, 1, 1)
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FIELD(CTRL, PRNGSRST, 0, 1)
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REG32(CTRL_2, 0xc)
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FIELD(CTRL_2, REPCOUNTTESTCUTOFF, 8, 9)
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FIELD(CTRL_2, RESERVED_7_5, 5, 3)
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FIELD(CTRL_2, DIT, 0, 5)
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REG32(CTRL_3, 0x10)
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FIELD(CTRL_3, ADAPTPROPTESTCUTOFF, 8, 10)
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FIELD(CTRL_3, DLEN, 0, 8)
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REG32(CTRL_4, 0x14)
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FIELD(CTRL_4, SINGLEBITRAW, 0, 1)
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REG32(EXT_SEED_0, 0x40)
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REG32(EXT_SEED_1, 0x44)
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REG32(EXT_SEED_2, 0x48)
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REG32(EXT_SEED_3, 0x4c)
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REG32(EXT_SEED_4, 0x50)
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REG32(EXT_SEED_5, 0x54)
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REG32(EXT_SEED_6, 0x58)
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REG32(EXT_SEED_7, 0x5c)
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REG32(EXT_SEED_8, 0x60)
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REG32(EXT_SEED_9, 0x64)
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REG32(EXT_SEED_10, 0x68)
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REG32(EXT_SEED_11, 0x6c)
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REG32(PER_STRNG_0, 0x80)
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REG32(PER_STRNG_1, 0x84)
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REG32(PER_STRNG_2, 0x88)
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REG32(PER_STRNG_3, 0x8c)
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REG32(PER_STRNG_4, 0x90)
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REG32(PER_STRNG_5, 0x94)
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REG32(PER_STRNG_6, 0x98)
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REG32(PER_STRNG_7, 0x9c)
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REG32(PER_STRNG_8, 0xa0)
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REG32(PER_STRNG_9, 0xa4)
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REG32(PER_STRNG_10, 0xa8)
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REG32(PER_STRNG_11, 0xac)
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REG32(CORE_OUTPUT, 0xc0)
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REG32(RESET, 0xd0)
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FIELD(RESET, VAL, 0, 1)
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REG32(OSC_EN, 0xd4)
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FIELD(OSC_EN, VAL, 0, 1)
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REG32(TRNG_ISR, 0xe0)
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FIELD(TRNG_ISR, SLVERR, 1, 1)
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FIELD(TRNG_ISR, CORE_INT, 0, 1)
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REG32(TRNG_IMR, 0xe4)
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FIELD(TRNG_IMR, SLVERR, 1, 1)
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FIELD(TRNG_IMR, CORE_INT, 0, 1)
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REG32(TRNG_IER, 0xe8)
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FIELD(TRNG_IER, SLVERR, 1, 1)
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FIELD(TRNG_IER, CORE_INT, 0, 1)
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REG32(TRNG_IDR, 0xec)
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FIELD(TRNG_IDR, SLVERR, 1, 1)
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FIELD(TRNG_IDR, CORE_INT, 0, 1)
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REG32(SLV_ERR_CTRL, 0xf0)
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FIELD(SLV_ERR_CTRL, ENABLE, 0, 1)
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#define R_MAX (R_SLV_ERR_CTRL + 1)
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QEMU_BUILD_BUG_ON(R_MAX * 4 != sizeof_field(XlnxVersalTRng, regs));
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#define TRNG_GUEST_ERROR(D, FMT, ...) \
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do { \
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g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
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qemu_log_mask(LOG_GUEST_ERROR, "%s: " FMT, p, ## __VA_ARGS__); \
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} while (0)
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#define TRNG_WARN(D, FMT, ...) \
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do { \
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g_autofree char *p = object_get_canonical_path(OBJECT(D)); \
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warn_report("%s: " FMT, p, ## __VA_ARGS__); \
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} while (0)
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static bool trng_older_than_v2(XlnxVersalTRng *s)
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{
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return s->hw_version < 0x0200;
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}
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static bool trng_in_reset(XlnxVersalTRng *s)
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{
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if (ARRAY_FIELD_EX32(s->regs, RESET, VAL)) {
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return true;
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}
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if (ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSRST)) {
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return true;
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}
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return false;
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}
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static bool trng_test_enabled(XlnxVersalTRng *s)
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{
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return ARRAY_FIELD_EX32(s->regs, CTRL, TSTMODE);
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}
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static bool trng_trss_enabled(XlnxVersalTRng *s)
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{
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if (trng_in_reset(s)) {
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return false;
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}
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if (!ARRAY_FIELD_EX32(s->regs, CTRL, TRSSEN)) {
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return false;
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}
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if (!ARRAY_FIELD_EX32(s->regs, OSC_EN, VAL)) {
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return false;
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}
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return true;
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}
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static void trng_seed_128(uint32_t *seed, uint64_t h00, uint64_t h64)
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{
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seed[0] = extract64(h00, 0, 32);
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seed[1] = extract64(h00, 32, 32);
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seed[2] = extract64(h64, 0, 32);
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seed[3] = extract64(h64, 32, 32);
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}
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static void trng_reseed(XlnxVersalTRng *s)
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{
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bool ext_seed = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGXS);
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bool pers_disabled = ARRAY_FIELD_EX32(s->regs, CTRL, PERSODISABLE);
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enum {
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U384_U8 = 384 / 8,
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U384_U32 = 384 / 32,
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};
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/*
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* Maximum seed length is len(personalized string) + len(ext seed).
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*
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* g_rand_set_seed_array() takes array of uint32 in host endian.
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*/
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guint32 gs[U384_U32 * 2], *seed = &gs[U384_U32];
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/*
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* A disabled personalized string is the same as
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* a string with all zeros.
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*
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* The device's hardware spec defines 3 modes (all selectable
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* by guest at will and at anytime):
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* 1) External seeding
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* This is a PRNG mode, in which the produced sequence shall
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* be reproducible if reseeded by the same 384-bit seed, as
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* supplied by guest software.
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* 2) Test seeding
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* This is a PRNG mode, in which the produced sequence shall
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* be reproducible if reseeded by a 128-bit test seed, as
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* supplied by guest software.
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* 3) Truly-random seeding
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* This is the TRNG mode, in which the produced sequence is
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* periodically reseeded by a crypto-strength entropy source.
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*
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* To assist debugging of certain classes of software defects,
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* this QEMU model implements a 4th mode,
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* 4) Forced PRNG
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* When in this mode, a reproducible sequence is generated
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* if software has selected the TRNG mode (mode 2).
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*
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* This emulation-only mode can only be selected by setting
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* the uint64 property 'forced-prng' to a non-zero value.
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* Guest software cannot select this mode.
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*/
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memset(gs, 0, sizeof(gs));
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if (!pers_disabled) {
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memcpy(gs, &s->regs[R_PER_STRNG_0], U384_U8);
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}
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if (ext_seed) {
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memcpy(seed, &s->regs[R_EXT_SEED_0], U384_U8);
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} else if (trng_test_enabled(s)) {
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trng_seed_128(seed, s->tst_seed[0], s->tst_seed[1]);
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} else if (s->forced_prng_seed) {
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s->forced_prng_count++;
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trng_seed_128(seed, s->forced_prng_count, s->forced_prng_seed);
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} else {
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qemu_guest_getrandom_nofail(seed, U384_U8);
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}
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g_rand_set_seed_array(s->prng, gs, ARRAY_SIZE(gs));
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s->rand_count = 0;
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s->rand_reseed = 1ULL << 48;
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}
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static void trng_regen(XlnxVersalTRng *s)
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{
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if (s->rand_reseed == 0) {
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TRNG_GUEST_ERROR(s, "Too many generations without a reseed");
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trng_reseed(s);
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}
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s->rand_reseed--;
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/*
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* In real hardware, each regen creates 256 bits, but QCNT
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* reports a max of 4.
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*/
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ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, 4);
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s->rand_count = 256 / 32;
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}
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static uint32_t trng_rdout(XlnxVersalTRng *s)
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{
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assert(s->rand_count);
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s->rand_count--;
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if (s->rand_count < 4) {
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ARRAY_FIELD_DP32(s->regs, STATUS, QCNT, s->rand_count);
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}
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return g_rand_int(s->prng);
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}
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static void trng_irq_update(XlnxVersalTRng *s)
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{
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bool pending = s->regs[R_TRNG_ISR] & ~s->regs[R_TRNG_IMR];
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qemu_set_irq(s->irq, pending);
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}
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static void trng_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
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trng_irq_update(s);
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}
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static uint64_t trng_ier_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
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uint32_t val = val64;
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s->regs[R_TRNG_IMR] &= ~val;
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trng_irq_update(s);
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return 0;
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}
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static uint64_t trng_idr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
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uint32_t val = val64;
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s->regs[R_TRNG_IMR] |= val;
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trng_irq_update(s);
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return 0;
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}
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static void trng_core_int_update(XlnxVersalTRng *s)
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{
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bool pending = false;
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uint32_t st = s->regs[R_STATUS];
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uint32_t en = s->regs[R_INT_CTRL];
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if (FIELD_EX32(st, STATUS, CERTF) && FIELD_EX32(en, INT_CTRL, CERTF_EN)) {
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pending = true;
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}
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if (FIELD_EX32(st, STATUS, DTF) && FIELD_EX32(en, INT_CTRL, DTF_EN)) {
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pending = true;
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}
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if (FIELD_EX32(st, STATUS, DONE) && FIELD_EX32(en, INT_CTRL, DONE_EN)) {
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pending = true;
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}
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ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, pending);
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trng_irq_update(s);
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}
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static void trng_int_ctrl_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
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uint32_t v32 = val64;
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uint32_t clr_mask = 0;
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if (FIELD_EX32(v32, INT_CTRL, CERTF_RST)) {
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clr_mask |= R_STATUS_CERTF_MASK;
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}
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if (FIELD_EX32(v32, INT_CTRL, DTF_RST)) {
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clr_mask |= R_STATUS_DTF_MASK;
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}
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if (FIELD_EX32(v32, INT_CTRL, DONE_RST)) {
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clr_mask |= R_STATUS_DONE_MASK;
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}
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s->regs[R_STATUS] &= ~clr_mask;
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trng_core_int_update(s);
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}
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static void trng_done(XlnxVersalTRng *s)
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{
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ARRAY_FIELD_DP32(s->regs, STATUS, DONE, true);
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trng_core_int_update(s);
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}
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static void trng_fault_event_set(XlnxVersalTRng *s, uint32_t events)
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{
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bool pending = false;
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/* Disabled TRSS cannot generate any fault event */
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if (!trng_trss_enabled(s)) {
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return;
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}
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if (FIELD_EX32(events, STATUS, CERTF)) {
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/* In older version, ERTU must be enabled explicitly to get CERTF */
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if (trng_older_than_v2(s) &&
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!ARRAY_FIELD_EX32(s->regs, CTRL, QERTUEN)) {
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TRNG_WARN(s, "CERTF injection ignored: ERTU disabled");
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} else {
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ARRAY_FIELD_DP32(s->regs, STATUS, CERTF, true);
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pending = true;
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}
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}
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if (FIELD_EX32(events, STATUS, DTF)) {
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ARRAY_FIELD_DP32(s->regs, STATUS, DTF, true);
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pending = true;
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}
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||||
|
||||
if (pending) {
|
||||
trng_core_int_update(s);
|
||||
}
|
||||
}
|
||||
|
||||
static void trng_soft_reset(XlnxVersalTRng *s)
|
||||
{
|
||||
s->rand_count = 0;
|
||||
s->regs[R_STATUS] = 0;
|
||||
|
||||
ARRAY_FIELD_DP32(s->regs, TRNG_ISR, CORE_INT, 0);
|
||||
}
|
||||
|
||||
static void trng_ctrl_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
|
||||
|
||||
if (trng_in_reset(s)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (FIELD_EX32(val64, CTRL, PRNGSRST)) {
|
||||
trng_soft_reset(s);
|
||||
trng_irq_update(s);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!FIELD_EX32(val64, CTRL, PRNGSTART)) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (FIELD_EX32(val64, CTRL, PRNGMODE)) {
|
||||
trng_regen(s);
|
||||
} else {
|
||||
trng_reseed(s);
|
||||
}
|
||||
|
||||
trng_done(s);
|
||||
}
|
||||
|
||||
static void trng_ctrl4_postw(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
|
||||
|
||||
/* Only applies to test mode with TRSS enabled */
|
||||
if (!trng_test_enabled(s) || !trng_trss_enabled(s)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Shift in a single bit. */
|
||||
s->tst_seed[1] <<= 1;
|
||||
s->tst_seed[1] |= s->tst_seed[0] >> 63;
|
||||
s->tst_seed[0] <<= 1;
|
||||
s->tst_seed[0] |= val64 & 1;
|
||||
|
||||
trng_reseed(s);
|
||||
trng_regen(s);
|
||||
}
|
||||
|
||||
static uint64_t trng_core_out_postr(RegisterInfo *reg, uint64_t val)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
|
||||
bool oneshot = ARRAY_FIELD_EX32(s->regs, CTRL, SINGLEGENMODE);
|
||||
bool start = ARRAY_FIELD_EX32(s->regs, CTRL, PRNGSTART);
|
||||
uint32_t r = 0xbad;
|
||||
|
||||
if (trng_in_reset(s)) {
|
||||
TRNG_GUEST_ERROR(s, "Reading random number while in reset!");
|
||||
return r;
|
||||
}
|
||||
|
||||
if (s->rand_count == 0) {
|
||||
TRNG_GUEST_ERROR(s, "Reading random number when unavailable!");
|
||||
return r;
|
||||
}
|
||||
|
||||
r = trng_rdout(s);
|
||||
|
||||
/* Automatic mode regenerates when half the output reg is empty. */
|
||||
if (!oneshot && start && s->rand_count <= 3) {
|
||||
trng_regen(s);
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static void trng_reset(XlnxVersalTRng *s)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
s->forced_prng_count = 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
|
||||
register_reset(&s->regs_info[i]);
|
||||
}
|
||||
trng_soft_reset(s);
|
||||
trng_irq_update(s);
|
||||
}
|
||||
|
||||
static uint64_t trng_reset_prew(RegisterInfo *reg, uint64_t val64)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg->opaque);
|
||||
|
||||
if (!ARRAY_FIELD_EX32(s->regs, RESET, VAL) &&
|
||||
FIELD_EX32(val64, RESET, VAL)) {
|
||||
trng_reset(s);
|
||||
}
|
||||
|
||||
return val64;
|
||||
}
|
||||
|
||||
static uint64_t trng_register_read(void *opaque, hwaddr addr, unsigned size)
|
||||
{
|
||||
/*
|
||||
* Guest provided seed and personalized strings cannot be
|
||||
* read back, and read attempts return value of A_STATUS.
|
||||
*/
|
||||
switch (addr) {
|
||||
case A_EXT_SEED_0 ... A_PER_STRNG_11:
|
||||
addr = A_STATUS;
|
||||
break;
|
||||
}
|
||||
|
||||
return register_read_memory(opaque, addr, size);
|
||||
}
|
||||
|
||||
static void trng_register_write(void *opaque, hwaddr addr,
|
||||
uint64_t value, unsigned size)
|
||||
{
|
||||
RegisterInfoArray *reg_array = opaque;
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(reg_array->r[0]->opaque);
|
||||
|
||||
if (trng_older_than_v2(s)) {
|
||||
switch (addr) {
|
||||
case A_CTRL:
|
||||
value = FIELD_DP64(value, CTRL, PERSODISABLE, 0);
|
||||
value = FIELD_DP64(value, CTRL, SINGLEGENMODE, 0);
|
||||
break;
|
||||
case A_CTRL_2:
|
||||
case A_CTRL_3:
|
||||
case A_CTRL_4:
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
switch (addr) {
|
||||
case A_CTRL:
|
||||
value = FIELD_DP64(value, CTRL, EATAU, 0);
|
||||
value = FIELD_DP64(value, CTRL, QERTUEN, 0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
register_write_memory(opaque, addr, value, size);
|
||||
}
|
||||
|
||||
static RegisterAccessInfo trng_regs_info[] = {
|
||||
{ .name = "INT_CTRL", .addr = A_INT_CTRL,
|
||||
.post_write = trng_int_ctrl_postw,
|
||||
},{ .name = "STATUS", .addr = A_STATUS,
|
||||
.ro = 0xfff,
|
||||
},{ .name = "CTRL", .addr = A_CTRL,
|
||||
.post_write = trng_ctrl_postw,
|
||||
},{ .name = "CTRL_2", .addr = A_CTRL_2,
|
||||
.reset = 0x210c,
|
||||
},{ .name = "CTRL_3", .addr = A_CTRL_3,
|
||||
.reset = 0x26f09,
|
||||
},{ .name = "CTRL_4", .addr = A_CTRL_4,
|
||||
.post_write = trng_ctrl4_postw,
|
||||
},{ .name = "EXT_SEED_0", .addr = A_EXT_SEED_0,
|
||||
},{ .name = "EXT_SEED_1", .addr = A_EXT_SEED_1,
|
||||
},{ .name = "EXT_SEED_2", .addr = A_EXT_SEED_2,
|
||||
},{ .name = "EXT_SEED_3", .addr = A_EXT_SEED_3,
|
||||
},{ .name = "EXT_SEED_4", .addr = A_EXT_SEED_4,
|
||||
},{ .name = "EXT_SEED_5", .addr = A_EXT_SEED_5,
|
||||
},{ .name = "EXT_SEED_6", .addr = A_EXT_SEED_6,
|
||||
},{ .name = "EXT_SEED_7", .addr = A_EXT_SEED_7,
|
||||
},{ .name = "EXT_SEED_8", .addr = A_EXT_SEED_8,
|
||||
},{ .name = "EXT_SEED_9", .addr = A_EXT_SEED_9,
|
||||
},{ .name = "EXT_SEED_10", .addr = A_EXT_SEED_10,
|
||||
},{ .name = "EXT_SEED_11", .addr = A_EXT_SEED_11,
|
||||
},{ .name = "PER_STRNG_0", .addr = A_PER_STRNG_0,
|
||||
},{ .name = "PER_STRNG_1", .addr = A_PER_STRNG_1,
|
||||
},{ .name = "PER_STRNG_2", .addr = A_PER_STRNG_2,
|
||||
},{ .name = "PER_STRNG_3", .addr = A_PER_STRNG_3,
|
||||
},{ .name = "PER_STRNG_4", .addr = A_PER_STRNG_4,
|
||||
},{ .name = "PER_STRNG_5", .addr = A_PER_STRNG_5,
|
||||
},{ .name = "PER_STRNG_6", .addr = A_PER_STRNG_6,
|
||||
},{ .name = "PER_STRNG_7", .addr = A_PER_STRNG_7,
|
||||
},{ .name = "PER_STRNG_8", .addr = A_PER_STRNG_8,
|
||||
},{ .name = "PER_STRNG_9", .addr = A_PER_STRNG_9,
|
||||
},{ .name = "PER_STRNG_10", .addr = A_PER_STRNG_10,
|
||||
},{ .name = "PER_STRNG_11", .addr = A_PER_STRNG_11,
|
||||
},{ .name = "CORE_OUTPUT", .addr = A_CORE_OUTPUT,
|
||||
.ro = 0xffffffff,
|
||||
.post_read = trng_core_out_postr,
|
||||
},{ .name = "RESET", .addr = A_RESET,
|
||||
.reset = 0x1,
|
||||
.pre_write = trng_reset_prew,
|
||||
},{ .name = "OSC_EN", .addr = A_OSC_EN,
|
||||
},{ .name = "TRNG_ISR", .addr = A_TRNG_ISR,
|
||||
.w1c = 0x3,
|
||||
.post_write = trng_isr_postw,
|
||||
},{ .name = "TRNG_IMR", .addr = A_TRNG_IMR,
|
||||
.reset = 0x3,
|
||||
.ro = 0x3,
|
||||
},{ .name = "TRNG_IER", .addr = A_TRNG_IER,
|
||||
.pre_write = trng_ier_prew,
|
||||
},{ .name = "TRNG_IDR", .addr = A_TRNG_IDR,
|
||||
.pre_write = trng_idr_prew,
|
||||
},{ .name = "SLV_ERR_CTRL", .addr = A_SLV_ERR_CTRL,
|
||||
}
|
||||
};
|
||||
|
||||
static const MemoryRegionOps trng_ops = {
|
||||
.read = trng_register_read,
|
||||
.write = trng_register_write,
|
||||
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||
.valid = {
|
||||
.min_access_size = 4,
|
||||
.max_access_size = 4,
|
||||
},
|
||||
};
|
||||
|
||||
static void trng_init(Object *obj)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(obj);
|
||||
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||||
RegisterInfoArray *reg_array;
|
||||
|
||||
reg_array =
|
||||
register_init_block32(DEVICE(obj), trng_regs_info,
|
||||
ARRAY_SIZE(trng_regs_info),
|
||||
s->regs_info, s->regs,
|
||||
&trng_ops,
|
||||
XLNX_VERSAL_TRNG_ERR_DEBUG,
|
||||
R_MAX * 4);
|
||||
|
||||
sysbus_init_mmio(sbd, ®_array->mem);
|
||||
sysbus_init_irq(sbd, &s->irq);
|
||||
|
||||
s->prng = g_rand_new();
|
||||
}
|
||||
|
||||
static void trng_unrealize(DeviceState *dev)
|
||||
{
|
||||
XlnxVersalTRng *s = XLNX_VERSAL_TRNG(dev);
|
||||
|
||||
g_rand_free(s->prng);
|
||||
s->prng = NULL;
|
||||
}
|
||||
|
||||
static void trng_reset_hold(Object *obj)
|
||||
{
|
||||
trng_reset(XLNX_VERSAL_TRNG(obj));
|
||||
}
|
||||
|
||||
static void trng_prop_fault_event_set(Object *obj, Visitor *v,
|
||||
const char *name, void *opaque,
|
||||
Error **errp)
|
||||
{
|
||||
Property *prop = opaque;
|
||||
uint32_t *events = object_field_prop_ptr(obj, prop);
|
||||
|
||||
visit_type_uint32(v, name, events, errp);
|
||||
if (*errp) {
|
||||
return;
|
||||
}
|
||||
|
||||
trng_fault_event_set(XLNX_VERSAL_TRNG(obj), *events);
|
||||
}
|
||||
|
||||
static const PropertyInfo trng_prop_fault_events = {
|
||||
.name = "uint32:bits",
|
||||
.description = "Set to trigger TRNG fault events",
|
||||
.set = trng_prop_fault_event_set,
|
||||
.realized_set_allowed = true,
|
||||
};
|
||||
|
||||
static PropertyInfo trng_prop_uint64; /* to extend qdev_prop_uint64 */
|
||||
|
||||
static Property trng_props[] = {
|
||||
DEFINE_PROP_UINT64("forced-prng", XlnxVersalTRng, forced_prng_seed, 0),
|
||||
DEFINE_PROP_UINT32("hw-version", XlnxVersalTRng, hw_version, 0x0200),
|
||||
DEFINE_PROP("fips-fault-events", XlnxVersalTRng, forced_faults,
|
||||
trng_prop_fault_events, uint32_t),
|
||||
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_trng = {
|
||||
.name = TYPE_XLNX_VERSAL_TRNG,
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(rand_count, XlnxVersalTRng),
|
||||
VMSTATE_UINT64(rand_reseed, XlnxVersalTRng),
|
||||
VMSTATE_UINT64(forced_prng_count, XlnxVersalTRng),
|
||||
VMSTATE_UINT64_ARRAY(tst_seed, XlnxVersalTRng, 2),
|
||||
VMSTATE_UINT32_ARRAY(regs, XlnxVersalTRng, R_MAX),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static void trng_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||||
|
||||
dc->vmsd = &vmstate_trng;
|
||||
dc->unrealize = trng_unrealize;
|
||||
rc->phases.hold = trng_reset_hold;
|
||||
|
||||
/* Clone uint64 property with set allowed after realized */
|
||||
trng_prop_uint64 = qdev_prop_uint64;
|
||||
trng_prop_uint64.realized_set_allowed = true;
|
||||
trng_props[0].info = &trng_prop_uint64;
|
||||
|
||||
device_class_set_props(dc, trng_props);
|
||||
}
|
||||
|
||||
static const TypeInfo trng_info = {
|
||||
.name = TYPE_XLNX_VERSAL_TRNG,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XlnxVersalTRng),
|
||||
.class_init = trng_class_init,
|
||||
.instance_init = trng_init,
|
||||
};
|
||||
|
||||
static void trng_register_types(void)
|
||||
{
|
||||
type_register_static(&trng_info);
|
||||
}
|
||||
|
||||
type_init(trng_register_types)
|
||||
58
include/hw/misc/xlnx-versal-trng.h
Normal file
58
include/hw/misc/xlnx-versal-trng.h
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Non-crypto strength model of the True Random Number Generator
|
||||
* in the AMD/Xilinx Versal device family.
|
||||
*
|
||||
* Copyright (c) 2017-2020 Xilinx Inc.
|
||||
* Copyright (c) 2023 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#ifndef XLNX_VERSAL_TRNG_H
|
||||
#define XLNX_VERSAL_TRNG_H
|
||||
|
||||
#include "hw/irq.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/register.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL_TRNG "xlnx.versal-trng"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalTRng, XLNX_VERSAL_TRNG);
|
||||
|
||||
#define RMAX_XLNX_VERSAL_TRNG ((0xf0 / 4) + 1)
|
||||
|
||||
typedef struct XlnxVersalTRng {
|
||||
SysBusDevice parent_obj;
|
||||
qemu_irq irq;
|
||||
GRand *prng;
|
||||
|
||||
uint32_t hw_version;
|
||||
uint32_t forced_faults;
|
||||
|
||||
uint32_t rand_count;
|
||||
uint64_t rand_reseed;
|
||||
|
||||
uint64_t forced_prng_seed;
|
||||
uint64_t forced_prng_count;
|
||||
uint64_t tst_seed[2];
|
||||
|
||||
uint32_t regs[RMAX_XLNX_VERSAL_TRNG];
|
||||
RegisterInfo regs_info[RMAX_XLNX_VERSAL_TRNG];
|
||||
} XlnxVersalTRng;
|
||||
|
||||
#undef RMAX_XLNX_VERSAL_TRNG
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user