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hw/arm_gic: Move gic_get_current_cpu into arm_gic.c

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Move the gic_get_current_cpu() function into arm_gic.c.
There are only two implementations: (1) "get the index
of the currently executing CPU", used by all multicore
GICs, and (2) "always 0", used by all GICs instantiated
with a single CPU interface (the Realview board GIC and
the v7M NVIC). So we can move this into the main GIC
source file.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
This commit is contained in:
Peter Maydell 2012-04-13 11:39:07 +00:00
parent 386e29554e
commit 926c4aff6e
7 changed files with 15 additions and 48 deletions
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8
hw/a15mpcore.c
View File

@ -20,14 +20,6 @@
#include "sysbus.h"
/* Configuration for arm_gic.c:
* how to ID current CPU
*/
static inline int gic_get_current_cpu(void)
{
return cpu_single_env->cpu_index;
}
#include "arm_gic.c"
/* A15MP private memory region. */

9
hw/a9mpcore.c
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@ -10,15 +10,6 @@
#include "sysbus.h"
/* Configuration for arm_gic.c:
* how to ID current CPU
*/
static inline int
gic_get_current_cpu(void)
{
return cpu_single_env->cpu_index;
}
#include "arm_gic.c"
/* A9MP private memory region. */

6
hw/arm11mpcore.c
View File

@ -10,12 +10,6 @@
#include "sysbus.h"
#include "qemu-timer.h"
static inline int
gic_get_current_cpu(void)
{
return cpu_single_env->cpu_index;
}
#include "arm_gic.c"
/* MPCore private memory region. */

20
hw/arm_gic.c
View File

@ -126,6 +126,16 @@ typedef struct gic_state
uint32_t num_irq;
} gic_state;
static inline int gic_get_current_cpu(gic_state *s)
{
#if NCPU > 1
if (s->num_cpu > 1) {
return cpu_single_env->cpu_index;
}
#endif
return 0;
}
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
static void gic_update(gic_state *s)
@ -285,7 +295,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
int cm;
int mask;
cpu = gic_get_current_cpu();
cpu = gic_get_current_cpu(s);
cm = 1 << cpu;
if (offset < 0x100) {
#ifndef NVIC
@ -420,7 +430,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
int i;
int cpu;
cpu = gic_get_current_cpu();
cpu = gic_get_current_cpu(s);
if (offset < 0x100) {
#ifdef NVIC
goto bad_reg;
@ -582,7 +592,7 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
int irq;
int mask;
cpu = gic_get_current_cpu();
cpu = gic_get_current_cpu(s);
irq = value & 0x3ff;
switch ((value >> 24) & 3) {
case 0:
@ -665,14 +675,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), addr);
return gic_cpu_read(s, gic_get_current_cpu(s), addr);
}
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), addr, value);
gic_cpu_write(s, gic_get_current_cpu(s), addr, value);
}
/* Wrappers to read/write the GIC CPU interface for a specific CPU.

7
hw/armv7m_nvic.c
View File

@ -17,13 +17,6 @@
#define NVIC 1
/* Only a single "CPU" interface is present. */
static inline int
gic_get_current_cpu(void)
{
return 0;
}
static uint32_t nvic_readl(void *opaque, uint32_t offset);
static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);

6
hw/exynos4210_gic.c
View File

@ -262,12 +262,6 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
/********* GIC part *********/
static inline int
gic_get_current_cpu(void)
{
return cpu_single_env->cpu_index;
}
#include "arm_gic.c"
typedef struct {

7
hw/realview_gic.c
View File

@ -9,13 +9,6 @@
#include "sysbus.h"
/* Only a single "CPU" interface is present. */
static inline int
gic_get_current_cpu(void)
{
return 0;
}
#include "arm_gic.c"
typedef struct {