From 9290f364c1f0c0a5a2ee8e03607f4804455c0d0e Mon Sep 17 00:00:00 2001 From: Alex Williamson Date: Thu, 5 Apr 2012 11:07:28 -0600 Subject: [PATCH] acpi_piix4: Re-define PCI hotplug eject register read The PCI hotplug eject register has always returned 0, so let's redefine it as a hotplug feature register. The existing model of using separate up & down read-only registers and an eject via write to this register becomes the base implementation. As we make use of new interfaces we'll set bits here to allow the BIOS and AML implementation to optimize for the platform implementation. Signed-off-by: Alex Williamson Signed-off-by: Michael S. Tsirkin --- docs/specs/acpi_pci_hotplug.txt | 12 ++++++++++-- hw/acpi_piix4.c | 7 ++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/docs/specs/acpi_pci_hotplug.txt b/docs/specs/acpi_pci_hotplug.txt index 1883d63061..a839434f31 100644 --- a/docs/specs/acpi_pci_hotplug.txt +++ b/docs/specs/acpi_pci_hotplug.txt @@ -27,8 +27,16 @@ events. Read-only. PCI device eject (IO port 0xae08-0xae0b, 4-byte access): ---------------------------------------- -Used by ACPI BIOS _EJ0 method to request device removal. One bit per slot. -Reads return 0. +Write: Used by ACPI BIOS _EJ0 method to request device removal. +One bit per slot. + +Read: Hotplug features register. Used by platform to identify features +available. Current base feature set (no bits set): + - Read-only "up" register @0xae00, 4-byte access, bit per slot + - Read-only "down" register @0xae04, 4-byte access, bit per slot + - Read/write "eject" register @0xae08, 4-byte access, + write: bit per slot eject, read: hotplug feature set + - Read-only hotplug capable register @0xae0c, 4-byte access, bit per slot PCI removability status (IO port 0xae0c-0xae0f, 4-byte access): ----------------------------------------------- diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 5d3b0ba11e..11c1f8532b 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -511,9 +511,10 @@ static uint32_t pci_down_read(void *opaque, uint32_t addr) return val; } -static uint32_t pciej_read(void *opaque, uint32_t addr) +static uint32_t pci_features_read(void *opaque, uint32_t addr) { - PIIX4_DPRINTF("pciej read %x\n", addr); + /* No feature defined yet */ + PIIX4_DPRINTF("pci_features_read %x\n", 0); return 0; } @@ -545,7 +546,7 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s) register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s); register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s); - register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, s); + register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s); register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);