tcg/aarch64: Support 128-bit load/store
With FEAT_LSE2, LDP/STP suffices. Without FEAT_LSE2, use LDXP+STXP 16-byte atomicity is required and LDP/STP otherwise. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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285a691fd2
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929124ec0b
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@ -13,6 +13,7 @@ C_O0_I1(r)
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C_O0_I2(r, rA)
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C_O0_I2(r, rA)
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C_O0_I2(rZ, r)
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C_O0_I2(rZ, r)
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C_O0_I2(w, r)
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C_O0_I2(w, r)
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C_O0_I3(rZ, rZ, r)
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C_O1_I1(r, r)
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C_O1_I1(r, r)
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C_O1_I1(w, r)
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C_O1_I1(w, r)
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C_O1_I1(w, w)
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C_O1_I1(w, w)
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@ -31,4 +32,5 @@ C_O1_I2(w, w, wO)
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C_O1_I2(w, w, wZ)
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C_O1_I2(w, w, wZ)
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C_O1_I3(w, w, w, w)
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C_O1_I3(w, w, w, w)
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C_O1_I4(r, r, rA, rZ, rZ)
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C_O1_I4(r, r, rA, rZ, rZ)
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C_O2_I1(r, r, r)
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C_O2_I4(r, r, rZ, rZ, rA, rMZ)
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C_O2_I4(r, r, rZ, rZ, rA, rMZ)
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@ -385,6 +385,10 @@ typedef enum {
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I3305_LDR_v64 = 0x5c000000,
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I3305_LDR_v64 = 0x5c000000,
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I3305_LDR_v128 = 0x9c000000,
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I3305_LDR_v128 = 0x9c000000,
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/* Load/store exclusive. */
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I3306_LDXP = 0xc8600000,
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I3306_STXP = 0xc8200000,
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/* Load/store register. Described here as 3.3.12, but the helper
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/* Load/store register. Described here as 3.3.12, but the helper
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that emits them can transform to 3.3.10 or 3.3.13. */
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that emits them can transform to 3.3.10 or 3.3.13. */
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I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
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I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
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@ -449,6 +453,9 @@ typedef enum {
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I3406_ADR = 0x10000000,
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I3406_ADR = 0x10000000,
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I3406_ADRP = 0x90000000,
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I3406_ADRP = 0x90000000,
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/* Add/subtract extended register instructions. */
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I3501_ADD = 0x0b200000,
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/* Add/subtract shifted register instructions (without a shift). */
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/* Add/subtract shifted register instructions (without a shift). */
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I3502_ADD = 0x0b000000,
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I3502_ADD = 0x0b000000,
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I3502_ADDS = 0x2b000000,
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I3502_ADDS = 0x2b000000,
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@ -619,6 +626,12 @@ static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,
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tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
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tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);
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}
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}
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static void tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, TCGReg rs,
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TCGReg rt, TCGReg rt2, TCGReg rn)
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{
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tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt);
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}
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static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
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static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
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TCGReg rt, int imm19)
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TCGReg rt, int imm19)
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{
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{
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@ -701,6 +714,14 @@ static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
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tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
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tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
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}
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}
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static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn,
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TCGType sf, TCGReg rd, TCGReg rn,
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TCGReg rm, int opt, int imm3)
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{
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tcg_out32(s, insn | sf << 31 | rm << 16 | opt << 13 |
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imm3 << 10 | rn << 5 | rd);
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}
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/* This function is for both 3.5.2 (Add/Subtract shifted register), for
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/* This function is for both 3.5.2 (Add/Subtract shifted register), for
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the rare occasion when we actually want to supply a shift amount. */
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the rare occasion when we actually want to supply a shift amount. */
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static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
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static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
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@ -1628,16 +1649,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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TCGType addr_type = s->addr_type;
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TCGType addr_type = s->addr_type;
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TCGLabelQemuLdst *ldst = NULL;
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TCGLabelQemuLdst *ldst = NULL;
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MemOp opc = get_memop(oi);
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MemOp opc = get_memop(oi);
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MemOp s_bits = opc & MO_SIZE;
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unsigned a_mask;
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unsigned a_mask;
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h->aa = atom_and_align_for_opc(s, opc,
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h->aa = atom_and_align_for_opc(s, opc,
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have_lse2 ? MO_ATOM_WITHIN16
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have_lse2 ? MO_ATOM_WITHIN16
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: MO_ATOM_IFALIGN,
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: MO_ATOM_IFALIGN,
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false);
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s_bits == MO_128);
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a_mask = (1 << h->aa.align) - 1;
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a_mask = (1 << h->aa.align) - 1;
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#ifdef CONFIG_SOFTMMU
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#ifdef CONFIG_SOFTMMU
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unsigned s_bits = opc & MO_SIZE;
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unsigned s_mask = (1u << s_bits) - 1;
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unsigned s_mask = (1u << s_bits) - 1;
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unsigned mem_index = get_mmuidx(oi);
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unsigned mem_index = get_mmuidx(oi);
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TCGReg addr_adj;
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TCGReg addr_adj;
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@ -1818,6 +1839,108 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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}
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}
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}
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}
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static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg addr_reg, MemOpIdx oi, bool is_ld)
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{
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TCGLabelQemuLdst *ldst;
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HostAddress h;
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TCGReg base;
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bool use_pair;
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ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
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/* Compose the final address, as LDP/STP have no indexing. */
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if (h.index == TCG_REG_XZR) {
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base = h.base;
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} else {
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base = TCG_REG_TMP2;
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if (h.index_ext == TCG_TYPE_I32) {
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/* add base, base, index, uxtw */
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tcg_out_insn(s, 3501, ADD, TCG_TYPE_I64, base,
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h.base, h.index, MO_32, 0);
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} else {
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/* add base, base, index */
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tcg_out_insn(s, 3502, ADD, 1, base, h.base, h.index);
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}
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}
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use_pair = h.aa.atom < MO_128 || have_lse2;
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if (!use_pair) {
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tcg_insn_unit *branch = NULL;
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TCGReg ll, lh, sl, sh;
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/*
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* If we have already checked for 16-byte alignment, that's all
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* we need. Otherwise we have determined that misaligned atomicity
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* may be handled with two 8-byte loads.
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*/
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if (h.aa.align < MO_128) {
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/*
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* TODO: align should be MO_64, so we only need test bit 3,
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* which means we could use TBNZ instead of ANDS+B_C.
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*/
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tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, 15);
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branch = s->code_ptr;
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tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
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use_pair = true;
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}
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if (is_ld) {
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/*
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* 16-byte atomicity without LSE2 requires LDXP+STXP loop:
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* ldxp lo, hi, [base]
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* stxp t0, lo, hi, [base]
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* cbnz t0, .-8
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* Require no overlap between data{lo,hi} and base.
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*/
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if (datalo == base || datahi == base) {
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tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_TMP2, base);
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base = TCG_REG_TMP2;
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}
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ll = sl = datalo;
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lh = sh = datahi;
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} else {
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/*
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* 16-byte atomicity without LSE2 requires LDXP+STXP loop:
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* 1: ldxp t0, t1, [base]
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* stxp t0, lo, hi, [base]
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* cbnz t0, 1b
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*/
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tcg_debug_assert(base != TCG_REG_TMP0 && base != TCG_REG_TMP1);
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ll = TCG_REG_TMP0;
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lh = TCG_REG_TMP1;
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sl = datalo;
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sh = datahi;
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}
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tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, ll, lh, base);
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tcg_out_insn(s, 3306, STXP, TCG_REG_TMP0, sl, sh, base);
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tcg_out_insn(s, 3201, CBNZ, 0, TCG_REG_TMP0, -2);
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if (use_pair) {
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/* "b .+8", branching across the one insn of use_pair. */
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tcg_out_insn(s, 3206, B, 2);
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reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr));
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}
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}
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if (use_pair) {
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if (is_ld) {
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tcg_out_insn(s, 3314, LDP, datalo, datahi, base, 0, 1, 0);
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} else {
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tcg_out_insn(s, 3314, STP, datalo, datahi, base, 0, 1, 0);
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}
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}
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if (ldst) {
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ldst->type = TCG_TYPE_I128;
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ldst->datalo_reg = datalo;
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ldst->datahi_reg = datahi;
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ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
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}
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}
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static const tcg_insn_unit *tb_ret_addr;
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static const tcg_insn_unit *tb_ret_addr;
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static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
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static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
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@ -2157,6 +2280,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_qemu_st_a64_i64:
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case INDEX_op_qemu_st_a64_i64:
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tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
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tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
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break;
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break;
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case INDEX_op_qemu_ld_a32_i128:
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case INDEX_op_qemu_ld_a64_i128:
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tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], true);
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break;
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case INDEX_op_qemu_st_a32_i128:
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case INDEX_op_qemu_st_a64_i128:
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tcg_out_qemu_ldst_i128(s, REG0(0), REG0(1), a2, args[3], false);
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break;
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case INDEX_op_bswap64_i64:
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case INDEX_op_bswap64_i64:
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tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
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tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1);
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@ -2796,11 +2927,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_qemu_ld_a32_i64:
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case INDEX_op_qemu_ld_a32_i64:
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case INDEX_op_qemu_ld_a64_i64:
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case INDEX_op_qemu_ld_a64_i64:
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return C_O1_I1(r, r);
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return C_O1_I1(r, r);
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case INDEX_op_qemu_ld_a32_i128:
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case INDEX_op_qemu_ld_a64_i128:
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return C_O2_I1(r, r, r);
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case INDEX_op_qemu_st_a32_i32:
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case INDEX_op_qemu_st_a32_i32:
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case INDEX_op_qemu_st_a64_i32:
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case INDEX_op_qemu_st_a64_i32:
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case INDEX_op_qemu_st_a32_i64:
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case INDEX_op_qemu_st_a32_i64:
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case INDEX_op_qemu_st_a64_i64:
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case INDEX_op_qemu_st_a64_i64:
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return C_O0_I2(rZ, r);
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return C_O0_I2(rZ, r);
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case INDEX_op_qemu_st_a32_i128:
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case INDEX_op_qemu_st_a64_i128:
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return C_O0_I3(rZ, rZ, r);
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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case INDEX_op_deposit_i64:
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@ -131,7 +131,16 @@ typedef enum {
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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/*
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* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
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* which requires writable pages. We must defer to the helper for user-only,
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* but in system mode all ram is writable for the host.
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*/
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#ifdef CONFIG_USER_ONLY
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#define TCG_TARGET_HAS_qemu_ldst_i128 have_lse2
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#else
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#define TCG_TARGET_HAS_qemu_ldst_i128 1
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#endif
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#define TCG_TARGET_HAS_v64 1
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#define TCG_TARGET_HAS_v64 1
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#define TCG_TARGET_HAS_v128 1
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#define TCG_TARGET_HAS_v128 1
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