xilinx_spi: Initial impl. of Xilinx SPI controller
Device model for xilinx XPS SPI controller (v2.0) Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
This commit is contained in:
Peter A. G. Crosthwaite
Peter Crosthwaite
parent
82a2499011
commit
929d1b52c4
@ -1,6 +1,7 @@
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obj-y = petalogix_s3adsp1800_mmu.o
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obj-y += petalogix_ml605_mmu.o
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obj-y += microblaze_boot.o
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obj-y += xilinx_spi.o
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obj-y += microblaze_pic_cpu.o
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obj-y += xilinx_ethlite.o
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383
hw/xilinx_spi.c
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383
hw/xilinx_spi.c
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@ -0,0 +1,383 @@
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/*
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* QEMU model of the Xilinx SPI Controller
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*
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* Copyright (C) 2010 Edgar E. Iglesias.
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* Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
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* Copyright (C) 2012 PetaLogix
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "sysemu.h"
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#include "qemu-log.h"
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#include "fifo.h"
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#include "ssi.h"
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#ifdef XILINX_SPI_ERR_DEBUG
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#define DB_PRINT(...) do { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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#define R_DGIER (0x1c / 4)
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#define R_DGIER_IE (1 << 31)
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#define R_IPISR (0x20 / 4)
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#define IRQ_DRR_NOT_EMPTY (1 << (31 - 23))
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#define IRQ_DRR_OVERRUN (1 << (31 - 26))
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#define IRQ_DRR_FULL (1 << (31 - 27))
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#define IRQ_TX_FF_HALF_EMPTY (1 << 6)
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#define IRQ_DTR_UNDERRUN (1 << 3)
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#define IRQ_DTR_EMPTY (1 << (31 - 29))
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#define R_IPIER (0x28 / 4)
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#define R_SRR (0x40 / 4)
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#define R_SPICR (0x60 / 4)
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#define R_SPICR_TXFF_RST (1 << 5)
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#define R_SPICR_RXFF_RST (1 << 6)
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#define R_SPICR_MTI (1 << 8)
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#define R_SPISR (0x64 / 4)
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#define SR_TX_FULL (1 << 3)
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#define SR_TX_EMPTY (1 << 2)
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#define SR_RX_FULL (1 << 1)
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#define SR_RX_EMPTY (1 << 0)
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#define R_SPIDTR (0x68 / 4)
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#define R_SPIDRR (0x6C / 4)
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#define R_SPISSR (0x70 / 4)
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#define R_TX_FF_OCY (0x74 / 4)
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#define R_RX_FF_OCY (0x78 / 4)
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#define R_MAX (0x7C / 4)
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#define FIFO_CAPACITY 256
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typedef struct XilinxSPI {
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SysBusDevice busdev;
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MemoryRegion mmio;
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qemu_irq irq;
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int irqline;
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uint8_t num_cs;
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qemu_irq *cs_lines;
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SSIBus *spi;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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uint32_t regs[R_MAX];
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} XilinxSPI;
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static void txfifo_reset(XilinxSPI *s)
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{
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fifo8_reset(&s->tx_fifo);
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s->regs[R_SPISR] &= ~SR_TX_FULL;
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s->regs[R_SPISR] |= SR_TX_EMPTY;
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}
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static void rxfifo_reset(XilinxSPI *s)
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{
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fifo8_reset(&s->rx_fifo);
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s->regs[R_SPISR] |= SR_RX_EMPTY;
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s->regs[R_SPISR] &= ~SR_RX_FULL;
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}
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static void xlx_spi_update_cs(XilinxSPI *s)
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{
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int i;
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for (i = 0; i < s->num_cs; ++i) {
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qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
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}
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}
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static void xlx_spi_update_irq(XilinxSPI *s)
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{
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uint32_t pending;
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s->regs[R_IPISR] |=
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(!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
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(fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
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pending = s->regs[R_IPISR] & s->regs[R_IPIER];
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pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
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pending = !!pending;
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/* This call lies right in the data paths so don't call the
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irq chain unless things really changed. */
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if (pending != s->irqline) {
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s->irqline = pending;
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DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
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pending, s->regs[R_IPISR], s->regs[R_IPIER]);
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qemu_set_irq(s->irq, pending);
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}
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}
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static void xlx_spi_do_reset(XilinxSPI *s)
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{
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memset(s->regs, 0, sizeof s->regs);
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rxfifo_reset(s);
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txfifo_reset(s);
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s->regs[R_SPISSR] = ~0;
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xlx_spi_update_irq(s);
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xlx_spi_update_cs(s);
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}
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static void xlx_spi_reset(DeviceState *d)
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{
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xlx_spi_do_reset(DO_UPCAST(XilinxSPI, busdev.qdev, d));
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}
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static inline int spi_master_enabled(XilinxSPI *s)
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{
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return !(s->regs[R_SPICR] & R_SPICR_MTI);
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}
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static void spi_flush_txfifo(XilinxSPI *s)
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{
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uint32_t tx;
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uint32_t rx;
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while (!fifo8_is_empty(&s->tx_fifo)) {
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tx = (uint32_t)fifo8_pop(&s->tx_fifo);
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DB_PRINT("data tx:%x\n", tx);
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rx = ssi_transfer(s->spi, tx);
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DB_PRINT("data rx:%x\n", rx);
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if (fifo8_is_full(&s->rx_fifo)) {
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s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
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} else {
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fifo8_push(&s->rx_fifo, (uint8_t)rx);
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if (fifo8_is_full(&s->rx_fifo)) {
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s->regs[R_SPISR] |= SR_RX_FULL;
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s->regs[R_IPISR] |= IRQ_DRR_FULL;
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}
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}
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s->regs[R_SPISR] &= ~SR_RX_EMPTY;
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s->regs[R_SPISR] &= ~SR_TX_FULL;
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s->regs[R_SPISR] |= SR_TX_EMPTY;
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s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
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s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
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}
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}
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static uint64_t
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spi_read(void *opaque, target_phys_addr_t addr, unsigned int size)
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{
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XilinxSPI *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_SPIDRR:
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if (fifo8_is_empty(&s->rx_fifo)) {
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DB_PRINT("Read from empty FIFO!\n");
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return 0xdeadbeef;
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}
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s->regs[R_SPISR] &= ~SR_RX_FULL;
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r = fifo8_pop(&s->rx_fifo);
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if (fifo8_is_empty(&s->rx_fifo)) {
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s->regs[R_SPISR] |= SR_RX_EMPTY;
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}
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break;
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case R_SPISR:
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r = s->regs[addr];
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break;
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default:
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if (addr < ARRAY_SIZE(s->regs)) {
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r = s->regs[addr];
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}
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break;
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}
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
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xlx_spi_update_irq(s);
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return r;
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}
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static void
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spi_write(void *opaque, target_phys_addr_t addr,
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uint64_t val64, unsigned int size)
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{
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XilinxSPI *s = opaque;
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uint32_t value = val64;
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DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
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addr >>= 2;
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switch (addr) {
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case R_SRR:
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if (value != 0xa) {
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DB_PRINT("Invalid write to SRR %x\n", value);
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} else {
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xlx_spi_do_reset(s);
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}
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break;
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case R_SPIDTR:
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s->regs[R_SPISR] &= ~SR_TX_EMPTY;
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fifo8_push(&s->tx_fifo, (uint8_t)value);
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if (fifo8_is_full(&s->tx_fifo)) {
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s->regs[R_SPISR] |= SR_TX_FULL;
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}
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if (!spi_master_enabled(s)) {
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goto done;
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} else {
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DB_PRINT("DTR and master enabled\n");
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}
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spi_flush_txfifo(s);
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break;
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case R_SPISR:
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DB_PRINT("Invalid write to SPISR %x\n", value);
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break;
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case R_IPISR:
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/* Toggle the bits. */
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s->regs[addr] ^= value;
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break;
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/* Slave Select Register. */
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case R_SPISSR:
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s->regs[addr] = value;
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xlx_spi_update_cs(s);
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break;
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case R_SPICR:
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/* FIXME: reset irq and sr state to empty queues. */
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if (value & R_SPICR_RXFF_RST) {
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rxfifo_reset(s);
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}
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if (value & R_SPICR_TXFF_RST) {
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txfifo_reset(s);
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}
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value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
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s->regs[addr] = value;
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if (!(value & R_SPICR_MTI)) {
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spi_flush_txfifo(s);
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}
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break;
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default:
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if (addr < ARRAY_SIZE(s->regs)) {
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s->regs[addr] = value;
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}
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break;
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}
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done:
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xlx_spi_update_irq(s);
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}
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static const MemoryRegionOps spi_ops = {
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.read = spi_read,
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.write = spi_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static int xilinx_spi_init(SysBusDevice *dev)
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{
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int i;
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XilinxSPI *s = FROM_SYSBUS(typeof(*s), dev);
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DB_PRINT("\n");
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sysbus_init_irq(dev, &s->irq);
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s->cs_lines = g_new(qemu_irq, s->num_cs);
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for (i = 0; i < s->num_cs; ++i) {
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sysbus_init_irq(dev, &s->cs_lines[i]);
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}
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memory_region_init_io(&s->mmio, &spi_ops, s, "xilinx-spi", R_MAX * 4);
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sysbus_init_mmio(dev, &s->mmio);
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s->irqline = -1;
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s->spi = ssi_create_bus(&dev->qdev, "spi");
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fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
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fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
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return 0;
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}
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static const VMStateDescription vmstate_xilinx_spi = {
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.name = "xilinx_spi",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_FIFO8(tx_fifo, XilinxSPI),
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VMSTATE_FIFO8(rx_fifo, XilinxSPI),
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VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property xilinx_spi_properties[] = {
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DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xilinx_spi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = xilinx_spi_init;
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dc->reset = xlx_spi_reset;
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dc->props = xilinx_spi_properties;
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dc->vmsd = &vmstate_xilinx_spi;
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}
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static TypeInfo xilinx_spi_info = {
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.name = "xlnx.xps-spi",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XilinxSPI),
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.class_init = xilinx_spi_class_init,
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};
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static void xilinx_spi_register_types(void)
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{
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type_register_static(&xilinx_spi_info);
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}
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type_init(xilinx_spi_register_types)
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