target/i386: reimplement 0x0f 0x60-0x6f, add AVX
These are both MMX and SSE/AVX instructions, except for vmovdqu. In both
cases the inputs and output is in s->ptr{0,1,2}, so the only difference
between MMX, SSE, and AVX is which helper to call.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini
parent
b98f886c8f
commit
92ec056a6b
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@ -135,6 +135,19 @@ static uint8_t get_modrm(DisasContext *s, CPUX86State *env)
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return s->modrm;
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}
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static inline const X86OpEntry *decode_by_prefix(DisasContext *s, const X86OpEntry entries[4])
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{
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if (s->prefix & PREFIX_REPNZ) {
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return &entries[3];
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} else if (s->prefix & PREFIX_REPZ) {
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return &entries[2];
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} else if (s->prefix & PREFIX_DATA) {
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return &entries[1];
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} else {
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return &entries[0];
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}
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}
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static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86GenFunc group17_gen[8] = {
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@ -144,6 +157,17 @@ static void decode_group17(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
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entry->gen = group17_gen[op];
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}
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static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F6F[4] = {
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X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
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{},
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};
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*entry = *decode_by_prefix(s, opcodes_0F6F);
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}
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static const X86OpEntry opcodes_0F38_00toEF[240] = {
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};
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@ -229,8 +253,26 @@ static void decode_0F3A(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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}
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static const X86OpEntry opcodes_0F[256] = {
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[0x60] = X86_OP_ENTRY3(PUNPCKLBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x61] = X86_OP_ENTRY3(PUNPCKLWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x62] = X86_OP_ENTRY3(PUNPCKLDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x63] = X86_OP_ENTRY3(PACKSSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x64] = X86_OP_ENTRY3(PCMPGTB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x65] = X86_OP_ENTRY3(PCMPGTW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x66] = X86_OP_ENTRY3(PCMPGTD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x67] = X86_OP_ENTRY3(PACKUSWB, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x38] = X86_OP_GROUP0(0F38),
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[0x3a] = X86_OP_GROUP0(0F3A),
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[0x68] = X86_OP_ENTRY3(PUNPCKHBW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x69] = X86_OP_ENTRY3(PUNPCKHWD, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x6a] = X86_OP_ENTRY3(PUNPCKHDQ, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x6b] = X86_OP_ENTRY3(PACKSSDW, V,x, H,x, W,x, vex4 mmx avx2_256 p_00_66),
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[0x6c] = X86_OP_ENTRY3(PUNPCKLQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
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[0x6d] = X86_OP_ENTRY3(PUNPCKHQDQ, V,x, H,x, W,x, vex4 p_66 avx2_256),
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[0x6e] = X86_OP_ENTRY3(MOVD_to, V,x, None,None, E,y, vex5 mmx p_00_66), /* wrong dest Vy on SDM! */
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[0x6f] = X86_OP_GROUP0(0F6F),
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};
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static void do_decode_0F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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@ -71,6 +71,56 @@ static inline int xmm_offset(MemOp ot)
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}
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}
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static int vector_reg_offset(X86DecodedOp *op)
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{
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assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE);
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if (op->unit == X86_OP_MMX) {
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return op->offset - mmx_offset(op->ot);
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} else {
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return op->offset - xmm_offset(op->ot);
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}
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}
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static int vector_elem_offset(X86DecodedOp *op, MemOp ot, int n)
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{
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int base_ofs = vector_reg_offset(op);
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switch(ot) {
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case MO_8:
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if (op->unit == X86_OP_MMX) {
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return base_ofs + offsetof(MMXReg, MMX_B(n));
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} else {
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return base_ofs + offsetof(ZMMReg, ZMM_B(n));
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}
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case MO_16:
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if (op->unit == X86_OP_MMX) {
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return base_ofs + offsetof(MMXReg, MMX_W(n));
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} else {
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return base_ofs + offsetof(ZMMReg, ZMM_W(n));
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}
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case MO_32:
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if (op->unit == X86_OP_MMX) {
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return base_ofs + offsetof(MMXReg, MMX_L(n));
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} else {
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return base_ofs + offsetof(ZMMReg, ZMM_L(n));
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}
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case MO_64:
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if (op->unit == X86_OP_MMX) {
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return base_ofs;
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} else {
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return base_ofs + offsetof(ZMMReg, ZMM_Q(n));
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}
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case MO_128:
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assert(op->unit == X86_OP_SSE);
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return base_ofs + offsetof(ZMMReg, ZMM_X(n));
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case MO_256:
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assert(op->unit == X86_OP_SSE);
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return base_ofs + offsetof(ZMMReg, ZMM_Y(n));
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default:
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g_assert_not_reached();
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}
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}
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static void compute_mmx_offset(X86DecodedOp *op)
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{
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if (!op->has_ea) {
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@ -183,6 +233,23 @@ static void gen_load(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v)
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}
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}
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static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn)
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{
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X86DecodedOp *op = &decode->op[opn];
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if (op->v_ptr) {
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return op->v_ptr;
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}
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op->v_ptr = tcg_temp_new_ptr();
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/* The temporary points to the MMXReg or ZMMReg. */
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tcg_gen_addi_ptr(op->v_ptr, cpu_env, vector_reg_offset(op));
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return op->v_ptr;
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}
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#define OP_PTR0 op_ptr(decode, 0)
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#define OP_PTR1 op_ptr(decode, 1)
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#define OP_PTR2 op_ptr(decode, 2)
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static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv v)
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{
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X86DecodedOp *op = &decode->op[opn];
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@ -216,6 +283,114 @@ static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv
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}
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}
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static inline int vector_len(DisasContext *s, X86DecodedInsn *decode)
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{
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if (decode->e.special == X86_SPECIAL_MMX &&
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!(s->prefix & (PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) {
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return 8;
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}
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return s->vex_l ? 32 : 16;
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}
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static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src_ofs)
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{
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MemOp ot = decode->op[0].ot;
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int vec_len = vector_len(s, decode);
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bool aligned = sse_needs_alignment(s, decode, ot);
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if (!decode->op[0].has_ea) {
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tcg_gen_gvec_mov(MO_64, decode->op[0].offset, src_ofs, vec_len, vec_len);
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return;
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}
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switch (ot) {
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case MO_64:
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gen_stq_env_A0(s, src_ofs);
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break;
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case MO_128:
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gen_sto_env_A0(s, src_ofs, aligned);
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break;
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case MO_256:
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gen_sty_env_A0(s, src_ofs, aligned);
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break;
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default:
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g_assert_not_reached();
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}
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}
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#define BINARY_INT_GVEC(uname, func, ...) \
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static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
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{ \
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int vec_len = vector_len(s, decode); \
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\
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func(__VA_ARGS__, \
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decode->op[0].offset, decode->op[1].offset, \
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decode->op[2].offset, vec_len, vec_len); \
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}
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BINARY_INT_GVEC(PCMPGTB, tcg_gen_gvec_cmp, TCG_COND_GT, MO_8)
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BINARY_INT_GVEC(PCMPGTW, tcg_gen_gvec_cmp, TCG_COND_GT, MO_16)
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BINARY_INT_GVEC(PCMPGTD, tcg_gen_gvec_cmp, TCG_COND_GT, MO_32)
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/*
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* 00 = p* Pq, Qq (if mmx not NULL; no VEX)
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* 66 = vp* Vx, Hx, Wx
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*
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* These are really the same encoding, because 1) V is the same as P when VEX.V
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* is not present 2) P and Q are the same as H and W apart from MM/XMM
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*/
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static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
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SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm)
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{
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assert(!!mmx == !!(decode->e.special == X86_SPECIAL_MMX));
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if (mmx && (s->prefix & PREFIX_VEX) && !(s->prefix & PREFIX_DATA)) {
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/* VEX encoding is not applicable to MMX instructions. */
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gen_illegal_opcode(s);
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return;
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}
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if (!(s->prefix & PREFIX_DATA)) {
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mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
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} else if (!s->vex_l) {
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xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
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} else {
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ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2);
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}
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}
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#define BINARY_INT_MMX(uname, lname) \
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static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
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{ \
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gen_binary_int_sse(s, env, decode, \
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gen_helper_##lname##_mmx, \
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gen_helper_##lname##_xmm, \
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gen_helper_##lname##_ymm); \
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}
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BINARY_INT_MMX(PUNPCKLBW, punpcklbw)
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BINARY_INT_MMX(PUNPCKLWD, punpcklwd)
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BINARY_INT_MMX(PUNPCKLDQ, punpckldq)
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BINARY_INT_MMX(PACKSSWB, packsswb)
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BINARY_INT_MMX(PACKUSWB, packuswb)
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BINARY_INT_MMX(PUNPCKHBW, punpckhbw)
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BINARY_INT_MMX(PUNPCKHWD, punpckhwd)
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BINARY_INT_MMX(PUNPCKHDQ, punpckhdq)
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BINARY_INT_MMX(PACKSSDW, packssdw)
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/* Instructions with no MMX equivalent. */
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#define BINARY_INT_SSE(uname, lname) \
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static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
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{ \
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gen_binary_int_sse(s, env, decode, \
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NULL, \
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gen_helper_##lname##_xmm, \
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gen_helper_##lname##_ymm); \
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}
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BINARY_INT_SSE(PUNPCKLQDQ, punpcklqdq)
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BINARY_INT_SSE(PUNPCKHQDQ, punpckhqdq)
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static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op)
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{
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TCGv carry_in = NULL;
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@ -383,6 +558,33 @@ static void gen_MOVBE(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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}
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}
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static void gen_MOVD_to(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[2].ot;
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int vec_len = vector_len(s, decode);
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int lo_ofs = vector_elem_offset(&decode->op[0], ot, 0);
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tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len, 0);
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switch (ot) {
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case MO_32:
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#ifdef TARGET_X86_64
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tcg_gen_st32_tl(s->T1, cpu_env, lo_ofs);
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break;
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case MO_64:
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#endif
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tcg_gen_st_tl(s->T1, cpu_env, lo_ofs);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void gen_MOVDQ(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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{
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gen_store_sse(s, decode, decode->op[2].offset);
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}
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static void gen_MULX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
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{
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MemOp ot = decode->op[0].ot;
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@ -2935,6 +2935,23 @@ static void gen_ldy_env_A0(DisasContext *s, int offset, bool align)
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tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3)));
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}
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static void gen_sty_env_A0(DisasContext *s, int offset, bool align)
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{
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int mem_index = s->mem_index;
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tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(0)));
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index,
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MO_LEUQ | (align ? MO_ALIGN_32 : 0));
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tcg_gen_addi_tl(s->tmp0, s->A0, 8);
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tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(1)));
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
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tcg_gen_addi_tl(s->tmp0, s->A0, 16);
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tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(2)));
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
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tcg_gen_addi_tl(s->tmp0, s->A0, 24);
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tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3)));
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tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ);
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}
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static inline void gen_op_movo(DisasContext *s, int d_offset, int s_offset)
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{
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tcg_gen_ld_i64(s->tmp1_i64, cpu_env, s_offset + offsetof(XMMReg, XMM_Q(0)));
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@ -4764,7 +4781,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
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#ifndef CONFIG_USER_ONLY
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use_new &= b <= limit;
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#endif
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if (use_new && 0) {
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if (use_new && (b >= 0x160 && b <= 0x16f)) {
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disas_insn_new(s, cpu, b + 0x100);
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return s->pc;
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}
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