target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l]
PowerISA v3.0B made tlbie[l] hypervisor privileged when PSR=0 and HR=1. To allow the check at translation time, we'll use the HR bit of LPCR to check the MMU mode instead of the PATE.HR. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210917114751.206845-3-matheus.ferst@eldorado.org.br> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -5517,7 +5517,15 @@ static void gen_tlbiel(DisasContext *ctx)
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#if defined(CONFIG_USER_ONLY)
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GEN_PRIV;
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#else
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CHK_SV;
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bool psr = (ctx->opcode >> 17) & 0x1;
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if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) {
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/*
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* tlbiel is privileged except when PSR=0 and HR=1, making it
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* hypervisor privileged.
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*/
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GEN_PRIV;
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}
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gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
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#endif /* defined(CONFIG_USER_ONLY) */
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@ -5529,12 +5537,20 @@ static void gen_tlbie(DisasContext *ctx)
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#if defined(CONFIG_USER_ONLY)
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GEN_PRIV;
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#else
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bool psr = (ctx->opcode >> 17) & 0x1;
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TCGv_i32 t1;
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if (ctx->gtse) {
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CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
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} else {
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CHK_HV; /* Else hypervisor privileged */
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if (ctx->pr) {
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/* tlbie is privileged... */
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GEN_PRIV;
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} else if (!ctx->hv) {
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if (!ctx->gtse || (!psr && ctx->hr)) {
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/*
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* ... except when GTSE=0 or when PSR=0 and HR=1, making it
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* hypervisor privileged.
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*/
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GEN_PRIV;
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}
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}
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if (NARROW_MODE(ctx)) {
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