arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180227143852.11175-21-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée
Peter Maydell
parent
7d4dd1a73a
commit
931931904c
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@ -11302,8 +11302,10 @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \
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CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
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CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
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FLOAT_CONVS(si, h, 16, )
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FLOAT_CONVS(si, s, 32, )
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FLOAT_CONVS(si, d, 64, )
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FLOAT_CONVS(ui, h, 16, u)
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FLOAT_CONVS(ui, s, 32, u)
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FLOAT_CONVS(ui, d, 64, u)
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@ -11386,6 +11388,8 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
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VFP_CONV_FIX(uh, s, 32, 32, uint16)
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VFP_CONV_FIX(ul, s, 32, 32, uint32)
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VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
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VFP_CONV_FIX_A64(sl, h, 16, 32, int32)
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VFP_CONV_FIX_A64(ul, h, 16, 32, uint32)
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#undef VFP_CONV_FIX
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#undef VFP_CONV_FIX_FLOAT
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#undef VFP_CONV_FLOAT_FIX_ROUND
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@ -120,17 +120,23 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env)
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DEF_HELPER_2(vfp_fcvtds, f64, f32, env)
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DEF_HELPER_2(vfp_fcvtsd, f32, f64, env)
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DEF_HELPER_2(vfp_uitoh, f16, i32, ptr)
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DEF_HELPER_2(vfp_uitos, f32, i32, ptr)
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DEF_HELPER_2(vfp_uitod, f64, i32, ptr)
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DEF_HELPER_2(vfp_sitoh, f16, i32, ptr)
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DEF_HELPER_2(vfp_sitos, f32, i32, ptr)
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DEF_HELPER_2(vfp_sitod, f64, i32, ptr)
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DEF_HELPER_2(vfp_touih, i32, f16, ptr)
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DEF_HELPER_2(vfp_touis, i32, f32, ptr)
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DEF_HELPER_2(vfp_touid, i32, f64, ptr)
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DEF_HELPER_2(vfp_touizh, i32, f16, ptr)
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DEF_HELPER_2(vfp_touizs, i32, f32, ptr)
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DEF_HELPER_2(vfp_touizd, i32, f64, ptr)
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DEF_HELPER_2(vfp_tosih, i32, f16, ptr)
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DEF_HELPER_2(vfp_tosis, i32, f32, ptr)
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DEF_HELPER_2(vfp_tosid, i32, f64, ptr)
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DEF_HELPER_2(vfp_tosizh, i32, f16, ptr)
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DEF_HELPER_2(vfp_tosizs, i32, f32, ptr)
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DEF_HELPER_2(vfp_tosizd, i32, f64, ptr)
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@ -142,6 +148,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr)
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DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr)
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DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
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DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
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DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
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DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
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DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
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DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
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DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
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@ -166,6 +174,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
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DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
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DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
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DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
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DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
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@ -6902,23 +6902,28 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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int elements, int is_signed,
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int fracbits, int size)
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{
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bool is_double = size == 3 ? true : false;
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TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
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TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
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TCGv_i64 tcg_int = tcg_temp_new_i64();
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TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
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TCGv_i32 tcg_shift = NULL;
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TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
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int pass;
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for (pass = 0; pass < elements; pass++) {
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read_vec_element(s, tcg_int, rn, pass, mop);
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if (fracbits || size == MO_64) {
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tcg_shift = tcg_const_i32(fracbits);
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}
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if (size == MO_64) {
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TCGv_i64 tcg_int64 = tcg_temp_new_i64();
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TCGv_i64 tcg_double = tcg_temp_new_i64();
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for (pass = 0; pass < elements; pass++) {
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read_vec_element(s, tcg_int64, rn, pass, mop);
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if (is_double) {
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TCGv_i64 tcg_double = tcg_temp_new_i64();
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if (is_signed) {
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gen_helper_vfp_sqtod(tcg_double, tcg_int,
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gen_helper_vfp_sqtod(tcg_double, tcg_int64,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_uqtod(tcg_double, tcg_int,
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gen_helper_vfp_uqtod(tcg_double, tcg_int64,
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tcg_shift, tcg_fpst);
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}
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if (elements == 1) {
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@ -6926,28 +6931,72 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
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} else {
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write_vec_element(s, tcg_double, rd, pass, MO_64);
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}
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tcg_temp_free_i64(tcg_double);
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} else {
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TCGv_i32 tcg_single = tcg_temp_new_i32();
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if (is_signed) {
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gen_helper_vfp_sqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_uqtos(tcg_single, tcg_int,
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tcg_shift, tcg_fpst);
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}
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if (elements == 1) {
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write_fp_sreg(s, rd, tcg_single);
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} else {
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write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
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}
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tcg_temp_free_i32(tcg_single);
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}
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tcg_temp_free_i64(tcg_int64);
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tcg_temp_free_i64(tcg_double);
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} else {
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TCGv_i32 tcg_int32 = tcg_temp_new_i32();
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TCGv_i32 tcg_float = tcg_temp_new_i32();
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for (pass = 0; pass < elements; pass++) {
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read_vec_element_i32(s, tcg_int32, rn, pass, mop);
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switch (size) {
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case MO_32:
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if (fracbits) {
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if (is_signed) {
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gen_helper_vfp_sltos(tcg_float, tcg_int32,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_ultos(tcg_float, tcg_int32,
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tcg_shift, tcg_fpst);
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}
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} else {
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if (is_signed) {
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gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
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} else {
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gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
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}
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}
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break;
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case MO_16:
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if (fracbits) {
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if (is_signed) {
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gen_helper_vfp_sltoh(tcg_float, tcg_int32,
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tcg_shift, tcg_fpst);
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} else {
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gen_helper_vfp_ultoh(tcg_float, tcg_int32,
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tcg_shift, tcg_fpst);
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}
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} else {
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if (is_signed) {
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gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
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} else {
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gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
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}
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}
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break;
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default:
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g_assert_not_reached();
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}
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if (elements == 1) {
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write_fp_sreg(s, rd, tcg_float);
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} else {
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write_vec_element_i32(s, tcg_float, rd, pass, size);
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}
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}
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tcg_temp_free_i32(tcg_int32);
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tcg_temp_free_i32(tcg_float);
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}
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tcg_temp_free_i64(tcg_int);
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tcg_temp_free_ptr(tcg_fpst);
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tcg_temp_free_i32(tcg_shift);
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if (tcg_shift) {
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tcg_temp_free_i32(tcg_shift);
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}
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clear_vec_high(s, elements << size == 16, rd);
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}
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@ -11236,6 +11285,23 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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rn = extract32(insn, 5, 5);
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switch (fpop) {
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case 0x1d: /* SCVTF */
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case 0x5d: /* UCVTF */
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{
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int elements;
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if (is_scalar) {
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elements = 1;
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} else {
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elements = (is_q ? 8 : 4);
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}
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if (!fp_access_check(s)) {
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return;
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}
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handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
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return;
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}
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break;
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case 0x2c: /* FCMGT (zero) */
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case 0x2d: /* FCMEQ (zero) */
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