Fix 'writeable' typos
We have about 30 instances of the typo/variant spelling 'writeable', and over 500 of the more common 'writable'. Standardize on the latter. Change produced with: sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep -il writeable) and then hand-undoing the instance in linux-headers/linux/kvm.h. Most of these changes are in comments or documentation; the exceptions are: * a local variable in accel/hvf/hvf-accel-ops.c * a local variable in accel/kvm/kvm-all.c * the PMCR_WRITABLE_MASK macro in target/arm/internals.h * the EPT_VIOLATION_GPA_WRITABLE macro in target/i386/hvf/vmcs.h (which is never used anywhere) * the AR_TYPE_WRITABLE_MASK macro in target/i386/hvf/vmx.h (which is never used anywhere) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 20220505095015.2714666-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
7ac610206a
commit
9323e79f10
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@ -120,12 +120,12 @@ static void hvf_set_phys_mem(MemoryRegionSection *section, bool add)
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{
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hvf_slot *mem;
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MemoryRegion *area = section->mr;
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bool writeable = !area->readonly && !area->rom_device;
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bool writable = !area->readonly && !area->rom_device;
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hv_memory_flags_t flags;
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uint64_t page_size = qemu_real_host_page_size();
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if (!memory_region_is_ram(area)) {
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if (writeable) {
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if (writable) {
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return;
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} else if (!memory_region_is_romd(area)) {
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/*
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@ -1346,13 +1346,13 @@ static void kvm_set_phys_mem(KVMMemoryListener *kml,
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KVMSlot *mem;
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int err;
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MemoryRegion *mr = section->mr;
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bool writeable = !mr->readonly && !mr->rom_device;
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bool writable = !mr->readonly && !mr->rom_device;
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hwaddr start_addr, size, slot_size, mr_offset;
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ram_addr_t ram_start_offset;
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void *ram;
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if (!memory_region_is_ram(mr)) {
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if (writeable || !kvm_readonly_mem_allowed) {
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if (writable || !kvm_readonly_mem_allowed) {
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return;
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} else if (!mr->romd_mode) {
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/* If the memory device is not in romd_mode, then we actually want
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@ -101,10 +101,10 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
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* Return true if the write fault has been handled, and should be re-tried.
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*
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* Note that it is important that we don't call page_unprotect() unless
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* this is really a "write to nonwriteable page" fault, because
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* this is really a "write to nonwritable page" fault, because
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* page_unprotect() assumes that if it is called for an access to
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* a page that's writeable this means we had two threads racing and
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* another thread got there first and already made the page writeable;
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* a page that's writable this means we had two threads racing and
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* another thread got there first and already made the page writable;
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* so we will retry the access. If we were to call page_unprotect()
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* for some other kind of fault that should really be passed to the
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* guest, we'd end up in an infinite loop of retrying the faulting access.
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@ -222,7 +222,7 @@ Virtio device config space
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:size: a 32-bit configuration space access size in bytes
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:flags: a 32-bit value:
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- 0: Vhost front-end messages used for writeable fields
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- 0: Vhost front-end messages used for writable fields
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- 1: Vhost front-end messages used for live migration
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:payload: Size bytes array holding the contents of the virtio
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@ -153,7 +153,7 @@ change the contents of the memory at runtime, specifically when starting a
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backed-up or snapshotted image. In order to do this, QEMU must know the
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address that has been allocated.
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The mechanism chosen for this memory sharing is writeable fw_cfg blobs.
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The mechanism chosen for this memory sharing is writable fw_cfg blobs.
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These are data object that are visible to both QEMU and guests, and are
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addressable as sequential files.
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@ -164,7 +164,7 @@ Two fw_cfg blobs are used in this case:
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/etc/vmgenid_guid - contains the actual VM Generation ID GUID
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- read-only to the guest
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/etc/vmgenid_addr - contains the address of the downloaded vmgenid blob
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- writeable by the guest
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- writable by the guest
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QEMU sends the following commands to the guest at startup:
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@ -249,7 +249,7 @@ void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker)
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for (i = 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) {
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/*
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* Initialize the value of read_ack_register to 1, so GHES can be
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* writeable after (re)boot.
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* writable after (re)boot.
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* ACPI 6.2: 18.3.2.8 Generic Hardware Error Source version 2
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* (GHESv2 - Type 10)
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*/
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@ -2047,7 +2047,7 @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
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cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR;
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}
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/* The only bit stored in icc_ctlr_el3 which is writeable is EOIMODE_EL3: */
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/* The only bit stored in icc_ctlr_el3 which is writable is EOIMODE_EL3: */
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mask = ICC_CTLR_EL3_EOIMODE_EL3;
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cs->icc_ctlr_el3 &= ~mask;
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@ -611,7 +611,7 @@ static bool gicd_writel(GICv3State *s, hwaddr offset,
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if (value & mask & GICD_CTLR_DS) {
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/* We just set DS, so the ARE_NS and EnG1S bits are now RES0.
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* Note that this is a one-way transition because if DS is set
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* then it's not writeable, so it can only go back to 0 with a
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* then it's not writable, so it can only go back to 0 with a
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* hardware reset.
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*/
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s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS);
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@ -257,7 +257,7 @@ static void gicr_write_vpendbaser(GICv3CPUState *cs, uint64_t newval)
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/*
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* The DIRTY bit is read-only and for us is always zero;
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* other fields are writeable.
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* other fields are writable.
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*/
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newval &= R_GICR_VPENDBASER_INNERCACHE_MASK |
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R_GICR_VPENDBASER_SHAREABILITY_MASK |
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@ -491,7 +491,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
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/* RAZ/WI for our implementation */
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return MEMTX_OK;
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case GICR_WAKER:
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/* Only the ProcessorSleep bit is writeable. When the guest sets
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/* Only the ProcessorSleep bit is writable. When the guest sets
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* it it requests that we transition the channel between the
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* redistributor and the cpu interface to quiescent, and that
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* we set the ChildrenAsleep bit once the inteface has reached the
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@ -463,7 +463,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
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/* Claim software interrupt bits */
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for (i = 0; i < swi->num_harts; i++) {
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RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
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/* We don't claim mip.SSIP because it is writeable by software */
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/* We don't claim mip.SSIP because it is writable by software */
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if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
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error_report("MSIP already claimed");
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exit(1);
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@ -646,7 +646,7 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
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}
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if (addr == APLIC_DOMAINCFG) {
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/* Only IE bit writeable at the moment */
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/* Only IE bit writable at the moment */
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value &= APLIC_DOMAINCFG_IE;
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aplic->domaincfg = value;
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} else if ((APLIC_SOURCECFG_BASE <= addr) &&
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@ -456,7 +456,7 @@ static int shpc_cap_add_config(PCIDevice *d, Error **errp)
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pci_set_byte(config + SHPC_CAP_CxP, 0);
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pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
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d->shpc->cap = config_offset;
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/* Make dword select and data writeable. */
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/* Make dword select and data writable. */
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pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
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pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
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return 0;
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@ -633,7 +633,7 @@ struct mfi_ctrl_props {
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* metadata and user data
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* 1=5%, 2=10%, 3=15% and so on
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*/
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uint8_t viewSpace; /* snapshot writeable VIEWs
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uint8_t viewSpace; /* snapshot writable VIEWs
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* capacity as a % of source LD
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* capacity. 0=READ only
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* 1=5%, 2=10%, 3=15% and so on
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@ -165,7 +165,7 @@ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
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}
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if (tte & IOMMU_TTE_DATA_W) {
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/* Writeable */
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/* Writable */
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ret.perm = IOMMU_RW;
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} else {
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ret.perm = IOMMU_RO;
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@ -324,7 +324,7 @@ static void sse_timer_write(void *opaque, hwaddr offset, uint64_t value,
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{
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uint32_t old_ctl = s->cntp_aival_ctl;
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/* EN bit is writeable; CLR bit is write-0-to-clear, write-1-ignored */
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/* EN bit is writable; CLR bit is write-0-to-clear, write-1-ignored */
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s->cntp_aival_ctl &= ~R_CNTP_AIVAL_CTL_EN_MASK;
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s->cntp_aival_ctl |= value & R_CNTP_AIVAL_CTL_EN_MASK;
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if (!(value & R_CNTP_AIVAL_CTL_CLR_MASK)) {
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@ -495,7 +495,7 @@ class QEMUMachine:
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"""
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# If we keep the console socket open, we may deadlock waiting
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# for QEMU to exit, while QEMU is waiting for the socket to
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# become writeable.
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# become writable.
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if self._console_socket is not None:
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self._console_socket.close()
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self._console_socket = None
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@ -118,7 +118,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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/*
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* Don't allow writing to XPSR.Exception as it can cause
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* a transition into or out of handler mode (it's not
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* writeable via the MSR insn so this is a reasonable
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* writable via the MSR insn so this is a reasonable
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* restriction). Other fields are safe to update.
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*/
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xpsr_write(env, tmp, ~XPSR_EXCP);
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@ -1411,8 +1411,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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}
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env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
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env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
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env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK;
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env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK);
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pmu_op_finish(env);
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}
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@ -978,8 +978,8 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
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}
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}
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env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
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env->cp15.c9_pmcr |= (val & PMCR_WRITEABLE_MASK);
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env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK;
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env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK);
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pmu_op_finish(env);
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break;
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@ -1280,10 +1280,10 @@ enum MVEECIState {
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#define PMCRP 0x2
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#define PMCRE 0x1
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/*
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* Mask of PMCR bits writeable by guest (not including WO bits like C, P,
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* Mask of PMCR bits writable by guest (not including WO bits like C, P,
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* which can be written as 1 to trigger behaviour but which stay RAZ).
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*/
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#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
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#define PMCR_WRITABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
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#define PMXEVTYPER_P 0x80000000
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#define PMXEVTYPER_U 0x40000000
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@ -103,7 +103,7 @@ static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
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/* Convert CPU model data from X86CPU object to a property dictionary
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* that can recreate exactly the same CPU model, including every
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* writeable QOM property.
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* writable QOM property.
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*/
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static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
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{
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@ -330,7 +330,7 @@
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#define EPT_VIOLATION_DATA_WRITE (1UL << 1)
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#define EPT_VIOLATION_INST_FETCH (1UL << 2)
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#define EPT_VIOLATION_GPA_READABLE (1UL << 3)
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#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4)
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#define EPT_VIOLATION_GPA_WRITABLE (1UL << 4)
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#define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5)
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#define EPT_VIOLATION_GLA_VALID (1UL << 7)
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#define EPT_VIOLATION_XLAT_VALID (1UL << 8)
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@ -80,7 +80,7 @@ static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl)
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#define AR_TYPE_ACCESSES_MASK 1
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#define AR_TYPE_READABLE_MASK (1 << 1)
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#define AR_TYPE_WRITEABLE_MASK (1 << 2)
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#define AR_TYPE_WRITABLE_MASK (1 << 2)
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#define AR_TYPE_CODE_MASK (1 << 3)
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#define AR_TYPE_MASK 0x0f
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#define AR_TYPE_BUSY_64_TSS 11
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@ -284,7 +284,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
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g_assert(!s390_is_pv());
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/*
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* As operand exceptions have a lower priority than access exceptions,
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* we check whether the memory area is writeable (injecting the
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* we check whether the memory area is writable (injecting the
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* access execption if it is not) first.
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*/
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if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) {
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@ -56,7 +56,7 @@
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*
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* - `ebx`: contains the physical memory address where the loader has placed
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* the boot start info structure.
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* - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
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* - `cr0`: bit 0 (PE) must be set. All the other writable bits are cleared.
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* - `cr4`: all bits are cleared.
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* - `cs `: must be a 32-bit read/execute code segment with a base of ‘0’
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* and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
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