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arm: Update infocenter.arm.com URLs 

Update infocenter.arm.com URLs for various pieces of Arm
documentation to the new developer.arm.com equivalents.  (There is a
redirection in place from the old URLs, but we might as well update
our comments in case the redirect ever disappears in future.)

This patch covers all the URLs which are not MPS2/SSE-200/IoTKit
related (those are dealt with in a different patch).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210205171456.19939-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-05 17:14:56 +00:00
parent 5385320c2b
commit 932a8d1f11
7 changed files with 16 additions and 13 deletions
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2
hw/arm/aspeed_ast2600.c
View File

@ -216,7 +216,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
/*
* ASPEED ast2600 has 0xf as cluster ID
*
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388e/CIHEBGFG.html
* https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
*/
static uint64_t aspeed_calc_affinity(int cpu)
{

4
hw/arm/musca.c
View File

@ -15,8 +15,8 @@
* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
* We model the A and B1 variants of this board, as described in the TRMs:
* http://infocenter.arm.com/help/topic/com.arm.doc.101107_0000_00_en/index.html
* http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/index.html
* https://developer.arm.com/documentation/101107/latest/
* https://developer.arm.com/documentation/101312/latest/
*/
#include "qemu/osdep.h"

2
hw/misc/arm_integrator_debug.c
View File

@ -6,7 +6,7 @@
* to this area.
*
* The real h/w is described at:
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
* https://developer.arm.com/documentation/dui0159/b/peripherals-and-interfaces/debug-leds-and-dip-switch-interface
*
* Copyright (c) 2013 Alex Bennée <alex@bennee.com>
*

7
hw/timer/arm_timer.c
View File

@ -185,10 +185,11 @@ static arm_timer_state *arm_timer_init(uint32_t freq)
return s;
}
/* ARM PrimeCell SP804 dual timer module.
/*
* ARM PrimeCell SP804 dual timer module.
* Docs at
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
*/
* https://developer.arm.com/documentation/ddi0271/latest/
*/
#define TYPE_SP804 "sp804"
OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804)

7
include/hw/dma/pl080.h
View File

@ -10,11 +10,12 @@
* (at your option) any later version.
*/
/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
/*
* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
* The PL080 TRM is:
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
* https://developer.arm.com/documentation/ddi0196/latest
* and the PL081 TRM is:
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
* https://developer.arm.com/documentation/ddi0218/latest
*
* QEMU interface:
* + sysbus IRQ 0: DMACINTR combined interrupt line

2
include/hw/misc/arm_integrator_debug.h
View File

@ -3,7 +3,7 @@
*
* Browse the data sheet:
*
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0159b/Babbfijf.html
* https://developer.arm.com/documentation/dui0159/b/peripherals-and-interfaces/debug-leds-and-dip-switch-interface
*
* Copyright (c) 2013 Alex Bennée <alex@bennee.com>
*

5
include/hw/ssi/pl022.h
View File

@ -9,9 +9,10 @@
* (at your option) any later version.
*/
/* This is a model of the Arm PrimeCell PL022 synchronous serial port.
/*
* This is a model of the Arm PrimeCell PL022 synchronous serial port.
* The PL022 TRM is:
* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0194h/DDI0194H_ssp_pl022_trm.pdf
* https://developer.arm.com/documentation/ddi0194/latest
*
* QEMU interface:
* + sysbus IRQ: SSPINTR combined interrupt line