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hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value

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When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.

Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
     chapter 21.7.3: Control Register (ECSPIx_CONREG)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com
[bmeng: add a 'common_reset' function that does most of reset operation]
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-29 21:23:17 +08:00 committed by Peter Maydell
parent 9c431a43a6
commit 93722b6f6a
1 changed files with 24 additions and 8 deletions
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32
hw/ssi/imx_spi.c
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@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
}
static void imx_spi_reset(DeviceState *dev)
static void imx_spi_common_reset(IMXSPIState *s)
{
IMXSPIState *s = IMX_SPI(dev);
int i;
DPRINTF("\n");
memset(s->regs, 0, sizeof(s->regs));
s->regs[ECSPI_STATREG] = 0x00000003;
for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
switch (i) {
case ECSPI_CONREG:
/* CONREG is not updated on soft reset */
break;
case ECSPI_STATREG:
s->regs[i] = 0x00000003;
break;
default:
s->regs[i] = 0;
break;
}
}
imx_spi_rxfifo_reset(s);
imx_spi_txfifo_reset(s);
@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev)
static void imx_spi_soft_reset(IMXSPIState *s)
{
imx_spi_reset(DEVICE(s));
imx_spi_common_reset(s);
imx_spi_update_irq(s);
}
static void imx_spi_reset(DeviceState *dev)
{
IMXSPIState *s = IMX_SPI(dev);
imx_spi_common_reset(s);
s->regs[ECSPI_CONREG] = 0;
}
static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
{
uint32_t value = 0;