hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
The function exynos4210_init_board_irqs() currently lives in exynos4210_gic.c, but it isn't really part of the exynos4210.gic device -- it is a function that implements (some of) the wiring up of interrupts between the SoC's GIC and combiner components. This means it fits better in exynos4210.c, which is the SoC-level code. Move it there. Similarly, exynos4210_git_irq() is used almost only in the SoC-level code, so move it too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
44068eabe0
commit
93afe073df
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@ -101,6 +101,208 @@
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#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
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#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
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enum ExtGicId {
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EXT_GIC_ID_MDMA_LCD0 = 66,
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EXT_GIC_ID_PDMA0,
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EXT_GIC_ID_PDMA1,
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EXT_GIC_ID_TIMER0,
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EXT_GIC_ID_TIMER1,
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EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3,
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EXT_GIC_ID_TIMER4,
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EXT_GIC_ID_MCT_L0,
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EXT_GIC_ID_WDT,
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EXT_GIC_ID_RTC_ALARM,
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EXT_GIC_ID_RTC_TIC,
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EXT_GIC_ID_GPIO_XB,
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EXT_GIC_ID_GPIO_XA,
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EXT_GIC_ID_MCT_L1,
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EXT_GIC_ID_IEM_APC,
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EXT_GIC_ID_IEM_IEC,
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EXT_GIC_ID_NFC,
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EXT_GIC_ID_UART0,
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EXT_GIC_ID_UART1,
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EXT_GIC_ID_UART2,
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EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4,
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EXT_GIC_ID_MCT_G0,
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EXT_GIC_ID_I2C0,
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EXT_GIC_ID_I2C1,
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EXT_GIC_ID_I2C2,
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EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4,
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EXT_GIC_ID_I2C5,
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EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7,
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EXT_GIC_ID_SPI0,
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EXT_GIC_ID_SPI1,
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EXT_GIC_ID_SPI2,
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EXT_GIC_ID_MCT_G1,
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EXT_GIC_ID_USB_HOST,
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EXT_GIC_ID_USB_DEVICE,
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EXT_GIC_ID_MODEMIF,
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EXT_GIC_ID_HSMMC0,
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EXT_GIC_ID_HSMMC1,
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EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3,
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EXT_GIC_ID_SDMMC,
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EXT_GIC_ID_MIPI_CSI_4LANE,
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EXT_GIC_ID_MIPI_DSI_4LANE,
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EXT_GIC_ID_MIPI_CSI_2LANE,
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EXT_GIC_ID_MIPI_DSI_2LANE,
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EXT_GIC_ID_ONENAND_AUDI,
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EXT_GIC_ID_ROTATOR,
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EXT_GIC_ID_FIMC0,
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EXT_GIC_ID_FIMC1,
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EXT_GIC_ID_FIMC2,
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EXT_GIC_ID_FIMC3,
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EXT_GIC_ID_JPEG,
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EXT_GIC_ID_2D,
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EXT_GIC_ID_PCIe,
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EXT_GIC_ID_MIXER,
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EXT_GIC_ID_HDMI,
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EXT_GIC_ID_HDMI_I2C,
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EXT_GIC_ID_MFC,
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EXT_GIC_ID_TVENC,
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};
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enum ExtInt {
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EXT_GIC_ID_EXTINT0 = 48,
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EXT_GIC_ID_EXTINT1,
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EXT_GIC_ID_EXTINT2,
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EXT_GIC_ID_EXTINT3,
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EXT_GIC_ID_EXTINT4,
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EXT_GIC_ID_EXTINT5,
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EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7,
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EXT_GIC_ID_EXTINT8,
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EXT_GIC_ID_EXTINT9,
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EXT_GIC_ID_EXTINT10,
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EXT_GIC_ID_EXTINT11,
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EXT_GIC_ID_EXTINT12,
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EXT_GIC_ID_EXTINT13,
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EXT_GIC_ID_EXTINT14,
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EXT_GIC_ID_EXTINT15
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};
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/*
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* External GIC sources which are not from External Interrupt Combiner or
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* External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
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* which is INTG16 in Internal Interrupt Combiner.
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*/
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static const uint32_t
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combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
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/* int combiner groups 16-19 */
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{ }, { }, { }, { },
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/* int combiner group 20 */
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{ 0, EXT_GIC_ID_MDMA_LCD0 },
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/* int combiner group 21 */
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{ EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
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/* int combiner group 22 */
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{ EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
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/* int combiner group 23 */
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{ EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
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/* int combiner group 24 */
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{ EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
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/* int combiner group 25 */
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{ EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
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/* int combiner group 26 */
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{ EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4 },
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/* int combiner group 27 */
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{ EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7 },
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/* int combiner group 28 */
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{ EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
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/* int combiner group 29 */
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{ EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
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/* int combiner group 30 */
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{ EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
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/* int combiner group 31 */
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{ EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
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/* int combiner group 32 */
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{ EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
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/* int combiner group 33 */
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{ EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
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/* int combiner group 34 */
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{ EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
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/* int combiner group 35 */
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{ 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* int combiner group 36 */
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{ EXT_GIC_ID_MIXER },
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/* int combiner group 37 */
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{ EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7 },
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/* groups 38-50 */
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{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
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/* int combiner group 51 */
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{ EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* group 52 */
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{ },
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/* int combiner group 53 */
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{ EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* groups 54-63 */
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{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
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};
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/*
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* Initialize board IRQs.
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* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
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*/
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static void exynos4210_init_board_irqs(Exynos4210State *s)
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{
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uint32_t grp, bit, irq_id, n;
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Exynos4210Irq *is = &s->irqs;
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for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
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irq_id = 0;
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if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
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n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
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/* MCT_G0 is passed to External GIC */
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irq_id = EXT_GIC_ID_MCT_G0;
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}
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if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
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n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
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/* MCT_G1 is passed to External and GIC */
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irq_id = EXT_GIC_ID_MCT_G1;
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}
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if (irq_id) {
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s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
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is->ext_gic_irq[irq_id - 32]);
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} else {
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s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
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is->ext_combiner_irq[n]);
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}
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}
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for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
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/* these IDs are passed to Internal Combiner and External GIC */
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grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
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bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
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irq_id = combiner_grp_to_gic_id[grp -
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EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
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if (irq_id) {
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s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
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is->ext_gic_irq[irq_id - 32]);
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}
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}
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}
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/*
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* Get IRQ number from exynos4210 IRQ subsystem stub.
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* To identify IRQ source use internal combiner group and bit number
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* grp - group number
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* bit - bit number inside group
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*/
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uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
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{
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return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
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}
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static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
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0x09, 0x00, 0x00, 0x00 };
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@ -30,154 +30,6 @@
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#include "hw/arm/exynos4210.h"
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#include "qom/object.h"
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enum ExtGicId {
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EXT_GIC_ID_MDMA_LCD0 = 66,
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EXT_GIC_ID_PDMA0,
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EXT_GIC_ID_PDMA1,
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EXT_GIC_ID_TIMER0,
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EXT_GIC_ID_TIMER1,
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EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3,
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EXT_GIC_ID_TIMER4,
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EXT_GIC_ID_MCT_L0,
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EXT_GIC_ID_WDT,
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EXT_GIC_ID_RTC_ALARM,
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EXT_GIC_ID_RTC_TIC,
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EXT_GIC_ID_GPIO_XB,
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EXT_GIC_ID_GPIO_XA,
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EXT_GIC_ID_MCT_L1,
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EXT_GIC_ID_IEM_APC,
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EXT_GIC_ID_IEM_IEC,
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EXT_GIC_ID_NFC,
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EXT_GIC_ID_UART0,
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EXT_GIC_ID_UART1,
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EXT_GIC_ID_UART2,
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EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4,
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EXT_GIC_ID_MCT_G0,
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EXT_GIC_ID_I2C0,
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EXT_GIC_ID_I2C1,
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EXT_GIC_ID_I2C2,
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EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4,
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EXT_GIC_ID_I2C5,
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EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7,
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EXT_GIC_ID_SPI0,
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EXT_GIC_ID_SPI1,
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EXT_GIC_ID_SPI2,
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EXT_GIC_ID_MCT_G1,
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EXT_GIC_ID_USB_HOST,
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EXT_GIC_ID_USB_DEVICE,
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EXT_GIC_ID_MODEMIF,
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EXT_GIC_ID_HSMMC0,
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EXT_GIC_ID_HSMMC1,
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EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3,
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EXT_GIC_ID_SDMMC,
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EXT_GIC_ID_MIPI_CSI_4LANE,
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EXT_GIC_ID_MIPI_DSI_4LANE,
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EXT_GIC_ID_MIPI_CSI_2LANE,
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EXT_GIC_ID_MIPI_DSI_2LANE,
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EXT_GIC_ID_ONENAND_AUDI,
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EXT_GIC_ID_ROTATOR,
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EXT_GIC_ID_FIMC0,
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EXT_GIC_ID_FIMC1,
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EXT_GIC_ID_FIMC2,
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EXT_GIC_ID_FIMC3,
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EXT_GIC_ID_JPEG,
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EXT_GIC_ID_2D,
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EXT_GIC_ID_PCIe,
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EXT_GIC_ID_MIXER,
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EXT_GIC_ID_HDMI,
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EXT_GIC_ID_HDMI_I2C,
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EXT_GIC_ID_MFC,
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EXT_GIC_ID_TVENC,
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};
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enum ExtInt {
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EXT_GIC_ID_EXTINT0 = 48,
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EXT_GIC_ID_EXTINT1,
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EXT_GIC_ID_EXTINT2,
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EXT_GIC_ID_EXTINT3,
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EXT_GIC_ID_EXTINT4,
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EXT_GIC_ID_EXTINT5,
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EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7,
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EXT_GIC_ID_EXTINT8,
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EXT_GIC_ID_EXTINT9,
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EXT_GIC_ID_EXTINT10,
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EXT_GIC_ID_EXTINT11,
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EXT_GIC_ID_EXTINT12,
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EXT_GIC_ID_EXTINT13,
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EXT_GIC_ID_EXTINT14,
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EXT_GIC_ID_EXTINT15
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};
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/*
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* External GIC sources which are not from External Interrupt Combiner or
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* External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
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* which is INTG16 in Internal Interrupt Combiner.
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*/
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static const uint32_t
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combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
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/* int combiner groups 16-19 */
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{ }, { }, { }, { },
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/* int combiner group 20 */
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{ 0, EXT_GIC_ID_MDMA_LCD0 },
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/* int combiner group 21 */
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{ EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
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/* int combiner group 22 */
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{ EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
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/* int combiner group 23 */
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{ EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
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/* int combiner group 24 */
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{ EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
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/* int combiner group 25 */
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{ EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
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/* int combiner group 26 */
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{ EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4 },
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/* int combiner group 27 */
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{ EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7 },
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/* int combiner group 28 */
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{ EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
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/* int combiner group 29 */
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{ EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
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/* int combiner group 30 */
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{ EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
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/* int combiner group 31 */
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{ EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
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/* int combiner group 32 */
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{ EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
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/* int combiner group 33 */
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{ EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
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/* int combiner group 34 */
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{ EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
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/* int combiner group 35 */
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{ 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* int combiner group 36 */
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{ EXT_GIC_ID_MIXER },
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/* int combiner group 37 */
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{ EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7 },
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/* groups 38-50 */
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{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
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/* int combiner group 51 */
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{ EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
|
||||
/* group 52 */
|
||||
{ },
|
||||
/* int combiner group 53 */
|
||||
{ EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
|
||||
/* groups 54-63 */
|
||||
{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
|
||||
};
|
||||
|
||||
#define EXYNOS4210_GIC_NIRQ 160
|
||||
|
||||
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
|
||||
|
|
@ -192,62 +44,6 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
|
|||
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
|
||||
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
|
||||
|
||||
/*
|
||||
* Initialize board IRQs.
|
||||
* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
|
||||
*/
|
||||
void exynos4210_init_board_irqs(Exynos4210State *s)
|
||||
{
|
||||
uint32_t grp, bit, irq_id, n;
|
||||
Exynos4210Irq *is = &s->irqs;
|
||||
|
||||
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
|
||||
irq_id = 0;
|
||||
if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
|
||||
n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
|
||||
/* MCT_G0 is passed to External GIC */
|
||||
irq_id = EXT_GIC_ID_MCT_G0;
|
||||
}
|
||||
if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
|
||||
n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
|
||||
/* MCT_G1 is passed to External and GIC */
|
||||
irq_id = EXT_GIC_ID_MCT_G1;
|
||||
}
|
||||
if (irq_id) {
|
||||
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
|
||||
is->ext_gic_irq[irq_id - 32]);
|
||||
} else {
|
||||
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
|
||||
is->ext_combiner_irq[n]);
|
||||
}
|
||||
}
|
||||
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
|
||||
/* these IDs are passed to Internal Combiner and External GIC */
|
||||
grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
|
||||
bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
|
||||
irq_id = combiner_grp_to_gic_id[grp -
|
||||
EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
|
||||
|
||||
if (irq_id) {
|
||||
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
|
||||
is->ext_gic_irq[irq_id - 32]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Get IRQ number from exynos4210 IRQ subsystem stub.
|
||||
* To identify IRQ source use internal combiner group and bit number
|
||||
* grp - group number
|
||||
* bit - bit number inside group
|
||||
*/
|
||||
uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
|
||||
{
|
||||
return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
|
||||
}
|
||||
|
||||
/********* GIC part *********/
|
||||
|
||||
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
|
||||
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
|
||||
|
||||
|
|
|
|||
|
|
@ -111,10 +111,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
|
|||
void exynos4210_write_secondary(ARMCPU *cpu,
|
||||
const struct arm_boot_info *info);
|
||||
|
||||
/* Initialize board IRQs.
|
||||
* These IRQs contain splitted Int/External Combiner and External Gic IRQs */
|
||||
void exynos4210_init_board_irqs(Exynos4210State *s);
|
||||
|
||||
/* Get IRQ number from exynos4210 IRQ subsystem stub.
|
||||
* To identify IRQ source use internal combiner group and bit number
|
||||
* grp - group number
|
||||
|
|
|
|||
Loading…
Reference in New Issue