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Change RTC time drift IRQ re-injection (Gleb Natapov) 

Currently IRQ are reinjected as soon as they are acknowledged to
the RTC, but Windows sometimes do acknowledgement in a loop with
global interrupt disabled waiting for interrupt to be cleared and
it does not mask RTC vector in PIC/APIC while doing this. In such
situation interrupt injection always fails and RTC interrupt is never
cleared.

Instead of reinjecting coalesced IRQs on acknowledgement the patch below
reinjects them by accelerating RTC clock a bit. This way RTC interrupt
is not constantly raced after coalesced interrupt.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7231 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori 2009-04-22 20:20:22 +00:00
parent 2ed51f5bfd
commit 93b665693d
1 changed files with 47 additions and 15 deletions
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62
hw/mc146818rtc.c
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@ -73,6 +73,7 @@ struct RTCState {
#ifdef TARGET_I386
uint32_t irq_coalesced;
uint32_t period;
QEMUTimer *coalesced_timer;
#endif
QEMUTimer *second_timer;
QEMUTimer *second_timer2;
@ -93,6 +94,37 @@ static void rtc_irq_raise(qemu_irq irq) {
static void rtc_set_time(RTCState *s);
static void rtc_copy_date(RTCState *s);
#ifdef TARGET_I386
static void rtc_coalesced_timer_update(RTCState *s)
{
if (s->irq_coalesced == 0) {
qemu_del_timer(s->coalesced_timer);
} else {
/* divide each RTC interval to 2 - 8 smaller intervals */
int c = MIN(s->irq_coalesced, 7) + 1;
int64_t next_clock = qemu_get_clock(vm_clock) +
muldiv64(s->period / c, ticks_per_sec, 32768);
qemu_mod_timer(s->coalesced_timer, next_clock);
}
}
static void rtc_coalesced_timer(void *opaque)
{
RTCState *s = opaque;
if (s->irq_coalesced != 0) {
apic_reset_irq_delivered();
s->cmos_data[RTC_REG_C] |= 0xc0;
rtc_irq_raise(s->irq);
if (apic_get_irq_delivered()) {
s->irq_coalesced--;
}
}
rtc_coalesced_timer_update(s);
}
#endif
static void rtc_timer_update(RTCState *s, int64_t current_time)
{
int period_code, period;
@ -138,14 +170,18 @@ static void rtc_periodic_timer(void *opaque)
RTCState *s = opaque;
rtc_timer_update(s, s->next_periodic_time);
#ifdef TARGET_I386
if ((s->cmos_data[RTC_REG_C] & 0xc0) && rtc_td_hack) {
s->irq_coalesced++;
return;
}
#endif
if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
s->cmos_data[RTC_REG_C] |= 0xc0;
#ifdef TARGET_I386
if(rtc_td_hack) {
apic_reset_irq_delivered();
rtc_irq_raise(s->irq);
if (!apic_get_irq_delivered()) {
s->irq_coalesced++;
rtc_coalesced_timer_update(s);
}
} else
#endif
rtc_irq_raise(s->irq);
}
if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
@ -415,15 +451,6 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
case RTC_REG_C:
ret = s->cmos_data[s->cmos_index];
qemu_irq_lower(s->irq);
#ifdef TARGET_I386
if(s->irq_coalesced) {
apic_reset_irq_delivered();
qemu_irq_raise(s->irq);
if (apic_get_irq_delivered())
s->irq_coalesced--;
break;
}
#endif
s->cmos_data[RTC_REG_C] = 0x00;
break;
default:
@ -536,6 +563,7 @@ static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
s->irq_coalesced = qemu_get_be32(f);
s->period = qemu_get_be32(f);
rtc_coalesced_timer_update(s);
return 0;
}
#endif
@ -558,6 +586,10 @@ RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year)
s->periodic_timer = qemu_new_timer(vm_clock,
rtc_periodic_timer, s);
#ifdef TARGET_I386
if (rtc_td_hack)
s->coalesced_timer = qemu_new_timer(vm_clock, rtc_coalesced_timer, s);
#endif
s->second_timer = qemu_new_timer(vm_clock,
rtc_update_second, s);
s->second_timer2 = qemu_new_timer(vm_clock,