hw/arm/iotkit: Rename IoTKit to ARMSSE
The Arm IoTKit was effectively the forerunner of a series of subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200: https://developer.arm.com/products/system-design/subsystems These are generally quite similar, though later iterations have extra devices that earlier ones do not. We want to add a model of the SSE-200, which means refactoring the IoTKit code into an abstract base class and subclasses (using the same design that the bcm283x SoC and Aspeed SoC family implementations do). As a first step, rename the IoTKit struct and QOM macros to ARMSSE, which is what we're going to name the base class. We temporarily retain TYPE_IOTKIT to avoid changing the code that instantiates a TYPE_IOTKIT device here and then changing it back again when it is re-introduced as a subclass. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
66647809f5
commit
93dbd10347
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@ -1,5 +1,5 @@
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/*
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* Arm IoT Kit
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* Arm SSE (Subsystems for Embedded): IoTKit
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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@ -24,7 +24,7 @@
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/* Create an alias region of @size bytes starting at @base
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* which mirrors the memory starting at @orig.
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*/
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static void make_alias(IoTKit *s, MemoryRegion *mr, const char *name,
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static void make_alias(ARMSSE *s, MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size, hwaddr orig)
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{
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memory_region_init_alias(mr, NULL, name, &s->container, orig, size);
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@ -41,18 +41,18 @@ static void irq_status_forwarder(void *opaque, int n, int level)
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static void nsccfg_handler(void *opaque, int n, int level)
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{
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IoTKit *s = IOTKIT(opaque);
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ARMSSE *s = ARMSSE(opaque);
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s->nsccfg = level;
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}
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static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum)
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static void iotkit_forward_ppc(ARMSSE *s, const char *ppcname, int ppcnum)
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{
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/* Each of the 4 AHB and 4 APB PPCs that might be present in a
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* system using the IoTKit has a collection of control lines which
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* system using the ARMSSE has a collection of control lines which
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* are provided by the security controller and which we want to
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* expose as control lines on the IoTKit device itself, so the
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* code using the IoTKit can wire them up to the PPCs.
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* expose as control lines on the ARMSSE device itself, so the
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* code using the ARMSSE can wire them up to the PPCs.
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*/
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SplitIRQ *splitter = &s->ppc_irq_splitter[ppcnum];
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DeviceState *iotkitdev = DEVICE(s);
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@ -91,7 +91,7 @@ static void iotkit_forward_ppc(IoTKit *s, const char *ppcname, int ppcnum)
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g_free(name);
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}
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static void iotkit_forward_sec_resp_cfg(IoTKit *s)
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static void iotkit_forward_sec_resp_cfg(ARMSSE *s)
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{
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/* Forward the 3rd output from the splitter device as a
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* named GPIO output of the iotkit object.
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@ -107,7 +107,7 @@ static void iotkit_forward_sec_resp_cfg(IoTKit *s)
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static void iotkit_init(Object *obj)
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{
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IoTKit *s = IOTKIT(obj);
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ARMSSE *s = ARMSSE(obj);
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int i;
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memory_region_init(&s->container, obj, "iotkit-container", UINT64_MAX);
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@ -175,20 +175,20 @@ static void iotkit_init(Object *obj)
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static void iotkit_exp_irq(void *opaque, int n, int level)
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{
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IoTKit *s = IOTKIT(opaque);
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ARMSSE *s = ARMSSE(opaque);
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qemu_set_irq(s->exp_irqs[n], level);
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}
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static void iotkit_mpcexp_status(void *opaque, int n, int level)
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{
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IoTKit *s = IOTKIT(opaque);
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ARMSSE *s = ARMSSE(opaque);
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qemu_set_irq(s->mpcexp_status_in[n], level);
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}
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static void iotkit_realize(DeviceState *dev, Error **errp)
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{
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IoTKit *s = IOTKIT(dev);
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ARMSSE *s = ARMSSE(dev);
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int i;
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MemoryRegion *mr;
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Error *err = NULL;
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@ -215,9 +215,9 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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* devices exist in both address spaces but with hard-wired security
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* permissions that will cause the CPU to fault for non-secure accesses.
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*
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* The IoTKit has an IDAU (Implementation Defined Access Unit),
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* The ARMSSE has an IDAU (Implementation Defined Access Unit),
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* which specifies hard-wired security permissions for different
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* areas of the physical address space. For the IoTKit IDAU, the
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* areas of the physical address space. For the ARMSSE IDAU, the
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* top 4 bits of the physical address are the IDAU region ID, and
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* if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
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* region, otherwise it is an S region.
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@ -239,7 +239,7 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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* 0x20000000..0x2007ffff 32KB FPGA block RAM
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* 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
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* 0x40000000..0x4000ffff base peripheral region 1
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* 0x40010000..0x4001ffff CPU peripherals (none for IoTKit)
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* 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
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* 0x40020000..0x4002ffff system control element peripherals
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* 0x40080000..0x400fffff base peripheral region 2
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* 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
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@ -306,8 +306,8 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in);
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/* The sec_resp_cfg output from the security controller must be split into
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* multiple lines, one for each of the PPCs within the IoTKit and one
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* that will be an output from the IoTKit to the system.
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* multiple lines, one for each of the PPCs within the ARMSSE and one
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* that will be an output from the ARMSSE to the system.
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*/
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object_property_set_int(OBJECT(&s->sec_resp_splitter), 3,
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"num-lines", &err);
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@ -475,7 +475,7 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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/* 0x40010000 .. 0x4001ffff: private CPU region: unused in IoTKit */
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/* 0x40020000 .. 0x4002ffff : IoTKit system control peripheral region */
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/* 0x40020000 .. 0x4002ffff : ARMSSE system control peripheral region */
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/* Devices behind APB PPC1:
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* 0x4002f000: S32K timer
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*/
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@ -558,7 +558,7 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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qdev_get_gpio_in(DEVICE(&s->nmi_orgate), 0));
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->s32kwatchdog), 0, 0x5002e000);
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/* 0x40080000 .. 0x4008ffff : IoTKit second Base peripheral region */
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/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
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qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
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object_property_set_bool(OBJECT(&s->nswatchdog), true, "realized", &err);
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@ -678,7 +678,7 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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* Expose our container region to the board model; this corresponds
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* to the AHB Slave Expansion ports which allow bus master devices
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* (eg DMA controllers) in the board model to make transactions into
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* devices in the IoTKit.
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* devices in the ARMSSE.
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*/
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
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@ -688,11 +688,12 @@ static void iotkit_realize(DeviceState *dev, Error **errp)
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static void iotkit_idau_check(IDAUInterface *ii, uint32_t address,
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int *iregion, bool *exempt, bool *ns, bool *nsc)
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{
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/* For IoTKit systems the IDAU responses are simple logical functions
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/*
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* For ARMSSE systems the IDAU responses are simple logical functions
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* of the address bits. The NSC attribute is guest-adjustable via the
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* NSCCFG register in the security controller.
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*/
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IoTKit *s = IOTKIT(ii);
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ARMSSE *s = ARMSSE(ii);
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int region = extract32(address, 28, 4);
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*ns = !(region & 1);
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@ -707,22 +708,22 @@ static const VMStateDescription iotkit_vmstate = {
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(nsccfg, IoTKit),
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VMSTATE_UINT32(nsccfg, ARMSSE),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property iotkit_properties[] = {
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DEFINE_PROP_LINK("memory", IoTKit, board_memory, TYPE_MEMORY_REGION,
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DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("EXP_NUMIRQ", IoTKit, exp_numirq, 64),
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DEFINE_PROP_UINT32("MAINCLK", IoTKit, mainclk_frq, 0),
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DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
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DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void iotkit_reset(DeviceState *dev)
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{
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IoTKit *s = IOTKIT(dev);
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ARMSSE *s = ARMSSE(dev);
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s->nsccfg = 0;
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}
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@ -740,9 +741,9 @@ static void iotkit_class_init(ObjectClass *klass, void *data)
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}
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static const TypeInfo iotkit_info = {
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.name = TYPE_IOTKIT,
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.name = TYPE_ARMSSE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IoTKit),
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.instance_size = sizeof(ARMSSE),
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.instance_init = iotkit_init,
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.class_init = iotkit_class_init,
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.interfaces = (InterfaceInfo[]) {
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@ -66,7 +66,7 @@ typedef struct {
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typedef struct {
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MachineState parent;
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IoTKit iotkit;
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ARMSSE iotkit;
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MemoryRegion psram;
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MemoryRegion ssram[3];
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MemoryRegion ssram1_m;
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@ -1,5 +1,5 @@
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/*
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* ARM IoT Kit
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* ARM SSE (Subsystems for Embedded): IoTKit
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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@ -9,7 +9,10 @@
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* (at your option) any later version.
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*/
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/* This is a model of the Arm IoT Kit which is documented in
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/*
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* This is a model of the Arm "Subsystems for Embedded" family of
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* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
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* SSE-200. Currently we model only the Arm IoT Kit which is documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* It contains:
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* a Cortex-M33
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@ -71,8 +74,15 @@
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#include "hw/or-irq.h"
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#include "hw/core/split-irq.h"
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#define TYPE_IOTKIT "iotkit"
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#define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT)
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#define TYPE_ARMSSE "iotkit"
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#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
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/*
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* For the moment TYPE_IOTKIT is a synonym for TYPE_ARMSSE (and the
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* latter's underlying name is left as "iotkit"); in a later
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* commit it will become a subclass of TYPE_ARMSSE.
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*/
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#define TYPE_IOTKIT TYPE_ARMSSE
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs
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@ -80,7 +90,7 @@
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#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
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#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
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typedef struct IoTKit {
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typedef struct ARMSSE {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -131,6 +141,6 @@ typedef struct IoTKit {
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MemoryRegion *board_memory;
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uint32_t exp_numirq;
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uint32_t mainclk_frq;
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} IoTKit;
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} ARMSSE;
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#endif
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